drm/msm/dsi: Correct io_start for MSM8994 (20nm PHY)

stable inclusion
from stable-5.10.20
commit 92a1514e0a5d426b6002e2302985193260985d52
bugzilla: 50608

--------------------------------

[ Upstream commit 33a7808c ]

The previous registers were *almost* correct, but instead of
PHYs, they were pointing at DSI PLLs, resulting in the PHY id
autodetection failing miserably.

Fixes: dcefc117 ("drm/msm/dsi: Add support for msm8x94")
Signed-off-by: NKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: NRob Clark <robdclark@chromium.org>
Signed-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>

drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c

@@ -139,7 +139,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
 		.disable = dsi_20nm_phy_disable,
 		.init = msm_dsi_phy_init_common,
 	},
-	.io_start = { 0xfd998300, 0xfd9a0300 },
+	.io_start = { 0xfd998500, 0xfd9a0500 },
 	.num_dsi_phy = 2,
 };