net/mlx5e: Configure IPsec packet offload flow steering
In packet offload mode, the HW is responsible to handle ESP headers, SPI numbers and trailers (ICV) together with different logic for RX and TX paths. In order to support packet offload mode, special logic is added to flow steering rules. Reviewed-by: NRaed Salem <raeds@nvidia.com> Reviewed-by: NSaeed Mahameed <saeedm@nvidia.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NSteffen Klassert <steffen.klassert@secunet.com>
Showing
想要评论请 注册 或 登录