提交 69f915cc 编写于 作者: T Tao Zhou 提交者: Alex Deucher

drm/amdgpu: loose check for umc poison mode

No need to check poison setting for each channel, check for umc0
channel0 is enough.
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 f9ed188d
...@@ -451,21 +451,13 @@ static uint32_t umc_v6_7_query_ras_poison_mode_per_channel( ...@@ -451,21 +451,13 @@ static uint32_t umc_v6_7_query_ras_poison_mode_per_channel(
static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev) static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev)
{ {
uint32_t umc_inst = 0;
uint32_t ch_inst = 0;
uint32_t umc_reg_offset = 0; uint32_t umc_reg_offset = 0;
LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { /* Enabling fatal error in umc instance0 channel0 will be
umc_reg_offset = get_umc_v6_7_reg_offset(adev, * considered as fatal error mode
umc_inst, */
ch_inst); umc_reg_offset = get_umc_v6_7_reg_offset(adev, 0, 0);
/* Enabling fatal error in one channel will be considered return !umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset);
as fatal error mode */
if (umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset))
return false;
}
return true;
} }
const struct amdgpu_ras_block_hw_ops umc_v6_7_ras_hw_ops = { const struct amdgpu_ras_block_hw_ops umc_v6_7_ras_hw_ops = {
......
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