drm/amd/display: Implement FIFO enable sequence on DCN32
[WHY?] FIFO enable sequence is incomplete as it is currently implemented in FW, and requires reset to prevent the FIFO to be enabled in an invalid state. This cannot be done until DIG FE is connected to the BE. [HOW?] Add FIFO enable sequence in driver for dcn32 with reset after DIG FE is connected to BE. Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NDillon Varone <Dillon.Varone@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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