clk: si5351: Fix clkout rate computation.

Rate was incorrectly computed because we read from wrong divider register.
Signed-off-by: NMarek Belisko <marek.belisko@streamunlimited.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org

drivers/clk/clk-si5351.c

@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
 	unsigned char reg;
 	unsigned char rdiv;
 
-	if (hwdata->num > 5)
+	if (hwdata->num <= 5)
 		reg = si5351_msynth_params_address(hwdata->num) + 2;
 	else
 		reg = SI5351_CLK6_7_OUTPUT_DIVIDER;