[media] omap3isp: Calculate vpclk_div for CSI-2
The video port clock is l3_ick divided by vpclk_div. This clock must be high enough for the external pixel rate. The video port requires two clock cycles to process a pixel. Signed-off-by: NSakari Ailus <sakari.ailus@iki.fi> Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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