net: spnic: initial commit the common module of Ramaxel NIC driver

Ramaxel inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4CBDP
CVE: NA

This initial commit contains Ramaxel's spnic common module
Signed-off-by: NYanling Song <songyl@ramaxel.com>
Reviewed-by: NZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>

arch/arm64/configs/openeuler_defconfig

@@ -7133,3 +7133,5 @@ CONFIG_RESCTRL=y
 CONFIG_ACPI_MPAM=y
 CONFIG_ETMEM_SCAN=m
 CONFIG_ETMEM_SWAP=m
+CONFIG_NET_VENDOR_RAMAXEL=y
+CONFIG_SPNIC=m

arch/x86/configs/openeuler_defconfig

@@ -8512,3 +8512,5 @@ CONFIG_ARCH_HAS_KCOV=y
 CONFIG_ETMEM_SCAN=m
 CONFIG_ETMEM_SWAP=m
 CONFIG_USERSWAP=y
+CONFIG_NET_VENDOR_RAMAXEL=y
+CONFIG_SPNIC=m

drivers/net/ethernet/Kconfig

@@ -159,6 +159,7 @@ source "drivers/net/ethernet/pasemi/Kconfig"
 source "drivers/net/ethernet/pensando/Kconfig"
 source "drivers/net/ethernet/qlogic/Kconfig"
 source "drivers/net/ethernet/qualcomm/Kconfig"
+source "drivers/net/ethernet/ramaxel/Kconfig"
 source "drivers/net/ethernet/rdc/Kconfig"
 source "drivers/net/ethernet/realtek/Kconfig"
 source "drivers/net/ethernet/renesas/Kconfig"

drivers/net/ethernet/Makefile

@@ -71,6 +71,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES) += packetengines/
 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
 obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/
+obj-$(CONFIG_NET_VENDOR_RAMAXEL) += ramaxel/
 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
 obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/
 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/

drivers/net/ethernet/ramaxel/Kconfig

+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Ramaxel driver configuration
+#
+
+config NET_VENDOR_RAMAXEL
+	bool "Ramaxel devices"
+	default y
+	help
+	If you have a network (Ethernet) card belonging to this class, say Y.
+	Note that the answer to this question doesn't directly affect the
+	kernel: saying N will just cause the configurator to skip all
+	the questions about Ramaxel cards. If you say Y, you will be asked
+	for your specific card in the following questions.
+
+if NET_VENDOR_RAMAXEL
+
+	source "drivers/net/ethernet/ramaxel/spnic/Kconfig"
+
+endif # NET_VENDOR_RAMAXEL

drivers/net/ethernet/ramaxel/Makefile

+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for the Ramaxel device drivers.
+#
+
+obj-$(CONFIG_SPNIC) += spnic/
\ No newline at end of file

drivers/net/ethernet/ramaxel/spnic/Kconfig

+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Ramaxel SPNIC driver configuration
+#
+
+config SPNIC
+	tristate "Ramaxel PCIE Network Interface Card"
+	default n
+	depends on PCI_MSI && NUMA && PCI_IOV && (X86 || ARM64)
+	help
+	This driver supports Ramaxel PCIE Ethernet cards.
+	To compile this driver as part of the kernel, choose Y here.
+	 If unsure, choose N.
+	The default is N.

drivers/net/ethernet/ramaxel/spnic/Makefile

+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_SPNIC) += spnic.o
+
+subdir-ccflags-y += -I$(src)/hw
+
+spnic-objs := hw/sphw_common.o \
+		hw/sphw_hwif.o \
+		hw/sphw_eqs.o \
+		hw/sphw_mbox.o \
+		hw/sphw_api_cmd.o \
+		hw/sphw_mgmt.o \
+		hw/sphw_wq.o \
+		hw/sphw_cmdq.o \
+		hw/sphw_prof_adap.o \
+		hw/sphw_hw_cfg.o \
+		hw/sphw_hw_comm.o \
+		hw/sphw_hwdev.o

drivers/net/ethernet/ramaxel/spnic/hw/sphw_api_cmd.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#ifndef SPHW_API_CMD_H
+#define SPHW_API_CMD_H
+
+#include "sphw_hwif.h"
+
+/*api_cmd_cell.ctrl structure*/
+#define SPHW_API_CMD_CELL_CTRL_CELL_LEN_SHIFT			0
+#define SPHW_API_CMD_CELL_CTRL_RD_DMA_ATTR_OFF_SHIFT		16
+#define SPHW_API_CMD_CELL_CTRL_WR_DMA_ATTR_OFF_SHIFT		24
+#define SPHW_API_CMD_CELL_CTRL_XOR_CHKSUM_SHIFT			56
+
+#define SPHW_API_CMD_CELL_CTRL_CELL_LEN_MASK			0x3FU
+#define SPHW_API_CMD_CELL_CTRL_RD_DMA_ATTR_OFF_MASK		0x3FU
+#define SPHW_API_CMD_CELL_CTRL_WR_DMA_ATTR_OFF_MASK		0x3FU
+#define SPHW_API_CMD_CELL_CTRL_XOR_CHKSUM_MASK			0xFFU
+
+#define SPHW_API_CMD_CELL_CTRL_SET(val, member)		\
+		((((u64)(val)) & SPHW_API_CMD_CELL_CTRL_##member##_MASK) << \
+		SPHW_API_CMD_CELL_CTRL_##member##_SHIFT)
+
+/*api_cmd_cell.desc structure*/
+#define SPHW_API_CMD_DESC_API_TYPE_SHIFT			0
+#define SPHW_API_CMD_DESC_RD_WR_SHIFT				1
+#define SPHW_API_CMD_DESC_MGMT_BYPASS_SHIFT			2
+#define SPHW_API_CMD_DESC_RESP_AEQE_EN_SHIFT			3
+#define SPHW_API_CMD_DESC_APICHN_RSVD_SHIFT			4
+#define SPHW_API_CMD_DESC_APICHN_CODE_SHIFT			6
+#define SPHW_API_CMD_DESC_PRIV_DATA_SHIFT			8
+#define SPHW_API_CMD_DESC_DEST_SHIFT				32
+#define SPHW_API_CMD_DESC_SIZE_SHIFT				40
+#define SPHW_API_CMD_DESC_XOR_CHKSUM_SHIFT			56
+
+#define SPHW_API_CMD_DESC_API_TYPE_MASK				0x1U
+#define SPHW_API_CMD_DESC_RD_WR_MASK				0x1U
+#define SPHW_API_CMD_DESC_MGMT_BYPASS_MASK			0x1U
+#define SPHW_API_CMD_DESC_RESP_AEQE_EN_MASK			0x1U
+#define SPHW_API_CMD_DESC_APICHN_RSVD_MASK			0x3U
+#define SPHW_API_CMD_DESC_APICHN_CODE_MASK			0x3U
+#define SPHW_API_CMD_DESC_PRIV_DATA_MASK			0xFFFFFFU
+#define SPHW_API_CMD_DESC_DEST_MASK				0x1FU
+#define SPHW_API_CMD_DESC_SIZE_MASK				0x7FFU
+#define SPHW_API_CMD_DESC_XOR_CHKSUM_MASK			0xFFU
+
+#define SPHW_API_CMD_DESC_SET(val, member)			\
+		((((u64)(val)) & SPHW_API_CMD_DESC_##member##_MASK) << \
+		SPHW_API_CMD_DESC_##member##_SHIFT)
+
+/*api_cmd_status header*/
+#define SPHW_API_CMD_STATUS_HEADER_VALID_SHIFT			0
+#define SPHW_API_CMD_STATUS_HEADER_CHAIN_ID_SHIFT		16
+
+#define SPHW_API_CMD_STATUS_HEADER_VALID_MASK			0xFFU
+#define SPHW_API_CMD_STATUS_HEADER_CHAIN_ID_MASK		0xFFU
+
+#define SPHW_API_CMD_STATUS_HEADER_GET(val, member)		\
+	      (((val) >> SPHW_API_CMD_STATUS_HEADER_##member##_SHIFT) & \
+	      SPHW_API_CMD_STATUS_HEADER_##member##_MASK)
+
+/*API_CHAIN_REQ CSR: 0x0020+api_idx*0x080*/
+#define SPHW_API_CMD_CHAIN_REQ_RESTART_SHIFT			1
+#define SPHW_API_CMD_CHAIN_REQ_WB_TRIGGER_SHIFT			2
+
+#define SPHW_API_CMD_CHAIN_REQ_RESTART_MASK			0x1U
+#define SPHW_API_CMD_CHAIN_REQ_WB_TRIGGER_MASK			0x1U
+
+#define SPHW_API_CMD_CHAIN_REQ_SET(val, member)		\
+	       (((val) & SPHW_API_CMD_CHAIN_REQ_##member##_MASK) << \
+	       SPHW_API_CMD_CHAIN_REQ_##member##_SHIFT)
+
+#define SPHW_API_CMD_CHAIN_REQ_GET(val, member)		\
+	      (((val) >> SPHW_API_CMD_CHAIN_REQ_##member##_SHIFT) & \
+	      SPHW_API_CMD_CHAIN_REQ_##member##_MASK)
+
+#define SPHW_API_CMD_CHAIN_REQ_CLEAR(val, member)		\
+	((val) & (~(SPHW_API_CMD_CHAIN_REQ_##member##_MASK	\
+		<< SPHW_API_CMD_CHAIN_REQ_##member##_SHIFT)))
+
+/*API_CHAIN_CTL CSR: 0x0014+api_idx*0x080*/
+#define SPHW_API_CMD_CHAIN_CTRL_RESTART_EN_SHIFT		1
+#define SPHW_API_CMD_CHAIN_CTRL_XOR_ERR_SHIFT			2
+#define SPHW_API_CMD_CHAIN_CTRL_AEQE_EN_SHIFT			4
+#define SPHW_API_CMD_CHAIN_CTRL_AEQ_ID_SHIFT			8
+#define SPHW_API_CMD_CHAIN_CTRL_XOR_CHK_EN_SHIFT		28
+#define SPHW_API_CMD_CHAIN_CTRL_CELL_SIZE_SHIFT			30
+
+#define SPHW_API_CMD_CHAIN_CTRL_RESTART_EN_MASK			0x1U
+#define SPHW_API_CMD_CHAIN_CTRL_XOR_ERR_MASK			0x1U
+#define SPHW_API_CMD_CHAIN_CTRL_AEQE_EN_MASK			0x1U
+#define SPHW_API_CMD_CHAIN_CTRL_AEQ_ID_MASK			0x3U
+#define SPHW_API_CMD_CHAIN_CTRL_XOR_CHK_EN_MASK			0x3U
+#define SPHW_API_CMD_CHAIN_CTRL_CELL_SIZE_MASK			0x3U
+
+#define SPHW_API_CMD_CHAIN_CTRL_SET(val, member)		\
+	(((val) & SPHW_API_CMD_CHAIN_CTRL_##member##_MASK) << \
+	SPHW_API_CMD_CHAIN_CTRL_##member##_SHIFT)
+
+#define SPHW_API_CMD_CHAIN_CTRL_CLEAR(val, member)		\
+	((val) & (~(SPHW_API_CMD_CHAIN_CTRL_##member##_MASK	\
+		<< SPHW_API_CMD_CHAIN_CTRL_##member##_SHIFT)))
+
+/*api_cmd rsp header*/
+#define SPHW_API_CMD_RESP_HEAD_VALID_SHIFT		0
+#define SPHW_API_CMD_RESP_HEAD_STATUS_SHIFT		8
+#define SPHW_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT		16
+#define SPHW_API_CMD_RESP_HEAD_RESP_LEN_SHIFT		24
+#define SPHW_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT	40
+
+#define SPHW_API_CMD_RESP_HEAD_VALID_MASK		0xFF
+#define SPHW_API_CMD_RESP_HEAD_STATUS_MASK		0xFFU
+#define SPHW_API_CMD_RESP_HEAD_CHAIN_ID_MASK		0xFFU
+#define SPHW_API_CMD_RESP_HEAD_RESP_LEN_MASK		0x1FFU
+#define SPHW_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK		0xFFFFFFU
+
+#define SPHW_API_CMD_RESP_HEAD_VALID_CODE		0xFF
+
+#define SPHW_API_CMD_RESP_HEADER_VALID(val)	\
+		(((val) & SPHW_API_CMD_RESP_HEAD_VALID_MASK) == \
+		SPHW_API_CMD_RESP_HEAD_VALID_CODE)
+
+#define SPHW_API_CMD_RESP_HEAD_GET(val, member) \
+		(((val) >> SPHW_API_CMD_RESP_HEAD_##member##_SHIFT) & \
+		SPHW_API_CMD_RESP_HEAD_##member##_MASK)
+
+#define SPHW_API_CMD_RESP_HEAD_CHAIN_ID(val)	\
+		(((val) >> SPHW_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT) & \
+		SPHW_API_CMD_RESP_HEAD_CHAIN_ID_MASK)
+
+#define SPHW_API_CMD_RESP_HEAD_DRIVER_PRIV(val)	\
+		((u16)(((val) >> SPHW_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT) & \
+		SPHW_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK))
+/*API_STATUS_0 CSR: 0x0030+api_idx*0x080*/
+#define SPHW_API_CMD_STATUS_CONS_IDX_MASK		0xFFFFFFU
+#define SPHW_API_CMD_STATUS_CONS_IDX_SHIFT		0
+
+#define SPHW_API_CMD_STATUS_FSM_MASK			0xFU
+#define SPHW_API_CMD_STATUS_FSM_SHIFT			24
+
+#define SPHW_API_CMD_STATUS_CHKSUM_ERR_MASK		0x3U
+#define SPHW_API_CMD_STATUS_CHKSUM_ERR_SHIFT		28
+
+#define SPHW_API_CMD_STATUS_CPLD_ERR_MASK		0x1U
+#define SPHW_API_CMD_STATUS_CPLD_ERR_SHIFT		30
+
+#define SPHW_API_CMD_STATUS_CONS_IDX(val) \
+		((val) & SPHW_API_CMD_STATUS_CONS_IDX_MASK)
+
+#define SPHW_API_CMD_STATUS_CHKSUM_ERR(val) \
+		(((val) >> SPHW_API_CMD_STATUS_CHKSUM_ERR_SHIFT) & \
+		SPHW_API_CMD_STATUS_CHKSUM_ERR_MASK)
+
+#define SPHW_API_CMD_STATUS_GET(val, member)			\
+		(((val) >> SPHW_API_CMD_STATUS_##member##_SHIFT) & \
+		SPHW_API_CMD_STATUS_##member##_MASK)
+
+enum sphw_api_cmd_chain_type {
+	/* write to mgmt cpu command with completion  */
+	SPHW_API_CMD_WRITE_TO_MGMT_CPU	= 2,
+	/* multi read command with completion notification - not used */
+	SPHW_API_CMD_MULTI_READ		= 3,
+	/* write command without completion notification */
+	SPHW_API_CMD_POLL_WRITE		= 4,
+	/* read command without completion notification */
+	SPHW_API_CMD_POLL_READ		= 5,
+	/* read from mgmt cpu command with completion */
+	SPHW_API_CMD_WRITE_ASYNC_TO_MGMT_CPU	= 6,
+	SPHW_API_CMD_MAX,
+};
+
+struct sphw_api_cmd_status {
+	u64 header;
+	u32 buf_desc;
+	u32 cell_addr_hi;
+	u32 cell_addr_lo;
+	u32 rsvd0;
+	u64 rsvd1;
+};
+
+/* HW struct */
+struct sphw_api_cmd_cell {
+	u64 ctrl;
+
+	/* address is 64 bit in HW struct */
+	u64 next_cell_paddr;
+
+	u64 desc;
+
+	/* HW struct */
+	union {
+		struct {
+			u64 hw_cmd_paddr;
+		} write;
+
+		struct {
+			u64 hw_wb_resp_paddr;
+			u64 hw_cmd_paddr;
+		} read;
+	};
+};
+
+struct sphw_api_cmd_resp_fmt {
+	u64				header;
+	u64				resp_data;
+};
+
+struct sphw_api_cmd_cell_ctxt {
+	struct sphw_api_cmd_cell	*cell_vaddr;
+
+	void				*api_cmd_vaddr;
+
+	struct sphw_api_cmd_resp_fmt	*resp;
+
+	struct completion		done;
+	int				status;
+
+	u32				saved_prod_idx;
+};
+
+struct sphw_api_cmd_chain_attr {
+	struct sphw_hwdev		*hwdev;
+	enum sphw_api_cmd_chain_type	chain_type;
+
+	u32				num_cells;
+	u16				rsp_size;
+	u16				cell_size;
+};
+
+struct sphw_api_cmd_chain {
+	struct sphw_hwdev		*hwdev;
+	enum sphw_api_cmd_chain_type	chain_type;
+
+	u32				num_cells;
+	u16				cell_size;
+	u16				rsp_size;
+
+	/* HW members is 24 bit format */
+	u32				prod_idx;
+	u32				cons_idx;
+
+	struct semaphore		sem;
+	/* Async cmd can not be scheduling */
+	spinlock_t			async_lock;
+
+	dma_addr_t			wb_status_paddr;
+	struct sphw_api_cmd_status	*wb_status;
+
+	dma_addr_t			head_cell_paddr;
+	struct sphw_api_cmd_cell	*head_node;
+
+	struct sphw_api_cmd_cell_ctxt	*cell_ctxt;
+	struct sphw_api_cmd_cell	*curr_node;
+
+	struct sphw_dma_addr_align	cells_addr;
+
+	u8				*cell_vaddr_base;
+	u64				cell_paddr_base;
+	u8				*rsp_vaddr_base;
+	u64				rsp_paddr_base;
+	u8				*buf_vaddr_base;
+	u64				buf_paddr_base;
+	u64				cell_size_align;
+	u64				rsp_size_align;
+	u64				buf_size_align;
+};
+
+int sphw_api_cmd_write(struct sphw_api_cmd_chain *chain, u8 node_id, const void *cmd, u16 size);
+
+int sphw_api_cmd_read(struct sphw_api_cmd_chain *chain, u8 node_id, const void *cmd, u16 size,
+		      void *ack, u16 ack_size);
+
+int sphw_api_cmd_init(struct sphw_hwdev *hwdev, struct sphw_api_cmd_chain **chain);
+
+void sphw_api_cmd_free(struct sphw_api_cmd_chain **chain);
+
+#endif

drivers/net/ethernet/ramaxel/spnic/hw/sphw_cfg_cmd.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#ifndef SPHW_CFG_CMD_H
+#define SPHW_CFG_CMD_H
+
+#include "sphw_mgmt_msg_base.h"
+
+enum cfg_cmd {
+	CFG_CMD_GET_DEV_CAP = 0,
+};
+
+struct cfg_cmd_dev_cap {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u16 rsvd1;
+
+	/* Public resources */
+	u8 host_id;
+	u8 ep_id;
+	u8 er_id;
+	u8 port_id;
+
+	u16 host_total_func;
+	u8 host_pf_num;
+	u8 pf_id_start;
+	u16 host_vf_num;
+	u16 vf_id_start;
+	u8 host_oq_id_mask_val;
+	u8 rsvd_host[3];
+
+	u16 svc_cap_en;
+	u16 max_vf;
+	u8 flexq_en;
+	u8 valid_cos_bitmap;
+	/* Reserved for func_valid_cos_bitmap */
+	u16 rsvd_func1;
+	u32 rsvd_func2;
+
+	u8 sf_svc_attr;
+	u8 func_sf_en;
+	u16 rsvd_sf;
+
+	u32 max_conn_num;
+	u16 max_stick2cache_num;
+	u16 max_bfilter_start_addr;
+	u16 bfilter_len;
+	u16 hash_bucket_num;
+
+	/* shared resource */
+	u8 host_sf_en;
+	u8 rsvd2_sr[3];
+	u32 host_pctx_num;
+	u32 host_ccxt_num;
+	u32 host_scq_num;
+	u32 host_srq_num;
+	u32 host_mpt_num;
+
+	/* l2nic */
+	u16 nic_max_sq_id;
+	u16 nic_max_rq_id;
+	u32 rsvd_nic[3];
+
+	/* RoCE */
+	u32 roce_max_qp;
+	u32 roce_max_cq;
+	u32 roce_max_srq;
+	u32 roce_max_mpt;
+	u32 roce_max_drc_qp;
+
+	u32 roce_cmtt_cl_start;
+	u32 roce_cmtt_cl_end;
+	u32 roce_cmtt_cl_size;
+
+	u32 roce_dmtt_cl_start;
+	u32 roce_dmtt_cl_end;
+	u32 roce_dmtt_cl_size;
+
+	u32 roce_wqe_cl_start;
+	u32 roce_wqe_cl_end;
+	u32 roce_wqe_cl_size;
+	u8 roce_srq_container_mode;
+	u8 rsvd_roce1[3];
+	u32 rsvd_roce2[5];
+
+	/* IPsec */
+	u32 ipsec_max_sactx;
+	u32 rsvd_ipsec[3];
+
+	/* OVS */
+	u32 ovs_max_qpc;
+	u16 fake_vf_start_id;
+	u8 fake_vf_num;
+	u8 rsvd_ovs1;
+	u32 rsvd_ovs2[2];
+
+	/* ToE */
+	u32 toe_max_pctx;
+	u32 toe_max_cq;
+	u16 toe_max_srq;
+	u16 toe_srq_id_start;
+	u16 toe_max_mpt;
+	u16 toe_max_cctxt;
+	u32 rsvd_toe[2];
+
+	/* FC */
+	u32 fc_max_pctx;
+	u32 fc_max_scq;
+	u32 fc_max_srq;
+
+	u32 fc_max_cctx;
+	u32 fc_cctx_id_start;
+
+	u8 fc_vp_id_start;
+	u8 fc_vp_id_end;
+	u8 rsvd_fc1[2];
+	u32 rsvd_fc2[5];
+
+	/* VBS */
+	u32 rsvd_vbs[4];
+
+	u32 rsvd_glb[11];
+};
+
+#endif

drivers/net/ethernet/ramaxel/spnic/hw/sphw_cmdq.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#ifndef SPHW_CMDQ_H
+#define SPHW_CMDQ_H
+
+#include "sphw_comm_msg_intf.h"
+
+#define SPHW_SCMD_DATA_LEN		16
+
+#define	SPHW_CMDQ_DEPTH		4096
+
+enum sphw_cmdq_type {
+	SPHW_CMDQ_SYNC,
+	SPHW_CMDQ_ASYNC,
+	SPHW_MAX_CMDQ_TYPES,
+};
+
+enum sphw_db_src_type {
+	SPHW_DB_SRC_CMDQ_TYPE,
+	SPHW_DB_SRC_L2NIC_SQ_TYPE,
+};
+
+enum sphw_cmdq_db_type {
+	SPHW_DB_SQ_RQ_TYPE,
+	SPHW_DB_CMDQ_TYPE,
+};
+
+/*hardware define: cmdq wqe*/
+struct sphw_cmdq_header {
+	u32	header_info;
+	u32	saved_data;
+};
+
+struct sphw_scmd_bufdesc {
+	u32	buf_len;
+	u32	rsvd;
+	u8	data[SPHW_SCMD_DATA_LEN];
+};
+
+struct sphw_lcmd_bufdesc {
+	struct sphw_sge		sge;
+	u32			rsvd1;
+	u64			saved_async_buf;
+	u64			rsvd3;
+};
+
+struct sphw_cmdq_db {
+	u32	db_head;
+	u32	db_info;
+};
+
+struct sphw_status {
+	u32	status_info;
+};
+
+struct sphw_ctrl {
+	u32	ctrl_info;
+};
+
+struct sphw_sge_resp {
+	struct sphw_sge	sge;
+	u32		rsvd;
+};
+
+struct sphw_cmdq_completion {
+	union {
+		struct sphw_sge_resp	sge_resp;
+		u64			direct_resp;
+	};
+};
+
+struct sphw_cmdq_wqe_scmd {
+	struct sphw_cmdq_header		header;
+	u64				rsvd;
+	struct sphw_status		status;
+	struct sphw_ctrl		ctrl;
+	struct sphw_cmdq_completion	completion;
+	struct sphw_scmd_bufdesc	buf_desc;
+};
+
+struct sphw_cmdq_wqe_lcmd {
+	struct sphw_cmdq_header		header;
+	struct sphw_status		status;
+	struct sphw_ctrl		ctrl;
+	struct sphw_cmdq_completion	completion;
+	struct sphw_lcmd_bufdesc	buf_desc;
+};
+
+struct sphw_cmdq_inline_wqe {
+	struct sphw_cmdq_wqe_scmd	wqe_scmd;
+};
+
+struct sphw_cmdq_wqe {
+	union {
+		struct sphw_cmdq_inline_wqe	inline_wqe;
+		struct sphw_cmdq_wqe_lcmd	wqe_lcmd;
+	};
+};
+
+struct sphw_cmdq_arm_bit {
+	u32	q_type;
+	u32	q_id;
+};
+
+enum sphw_cmdq_status {
+	SPHW_CMDQ_ENABLE = BIT(0),
+};
+
+enum sphw_cmdq_cmd_type {
+	SPHW_CMD_TYPE_NONE,
+	SPHW_CMD_TYPE_SET_ARM,
+	SPHW_CMD_TYPE_DIRECT_RESP,
+	SPHW_CMD_TYPE_SGE_RESP,
+	SPHW_CMD_TYPE_ASYNC,
+	SPHW_CMD_TYPE_FAKE_TIMEOUT,
+	SPHW_CMD_TYPE_TIMEOUT,
+	SPHW_CMD_TYPE_FORCE_STOP,
+};
+
+struct sphw_cmdq_cmd_info {
+	enum sphw_cmdq_cmd_type		cmd_type;
+	u16				channel;
+
+	struct completion		*done;
+	int				*errcode;
+	int				*cmpt_code;
+	u64				*direct_resp;
+	u64				cmdq_msg_id;
+
+	struct sphw_cmd_buf		*buf_in;
+	struct sphw_cmd_buf		*buf_out;
+};
+
+struct sphw_cmdq {
+	struct sphw_wq			wq;
+
+	enum sphw_cmdq_type		cmdq_type;
+	int				wrapped;
+
+	/* spinlock for send cmdq commands */
+	spinlock_t			cmdq_lock;
+
+	/* doorbell area */
+	u8 __iomem			*db_base;
+
+	struct cmdq_ctxt_info		cmdq_ctxt;
+
+	struct sphw_cmdq_cmd_info	*cmd_infos;
+
+	struct sphw_hwdev		*hwdev;
+};
+
+struct sphw_cmdqs {
+	struct sphw_hwdev		*hwdev;
+
+	struct pci_pool			*cmd_buf_pool;
+
+	/* All cmdq's CLA of a VF occupy a PAGE when cmdq wq is 1-level CLA */
+	dma_addr_t			wq_block_paddr;
+	void				*wq_block_vaddr;
+	struct sphw_cmdq		cmdq[SPHW_MAX_CMDQ_TYPES];
+
+	u32				status;
+	u32				disable_flag;
+
+	bool				lock_channel_en;
+	unsigned long			channel_stop;
+};
+
+enum sphw_set_arm_type {
+	SPHW_SET_ARM_CMDQ,
+	SPHW_SET_ARM_SQ,
+	SPHW_SET_ARM_TYPE_NUM,
+};
+
+int sphw_set_arm_bit(void *hwdev, enum sphw_set_arm_type q_type, u16 q_id);
+
+void sphw_cmdq_ceq_handler(void *hwdev, u32 ceqe_data);
+
+int sphw_reinit_cmdq_ctxts(struct sphw_hwdev *hwdev);
+
+bool sphw_cmdq_idle(struct sphw_cmdq *cmdq);
+
+int sphw_cmdqs_init(struct sphw_hwdev *hwdev);
+
+void sphw_cmdqs_free(struct sphw_hwdev *hwdev);
+
+void sphw_cmdq_flush_cmd(struct sphw_hwdev *hwdev, struct sphw_cmdq *cmdq);
+
+int sphw_cmdq_set_channel_status(struct sphw_hwdev *hwdev, u16 channel, bool enable);
+
+void sphw_cmdq_enable_channel_lock(struct sphw_hwdev *hwdev, bool enable);
+
+#endif

drivers/net/ethernet/ramaxel/spnic/hw/sphw_comm_cmd.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#ifndef SPHW_COMMON_CMD_H
+#define SPHW_COMMON_CMD_H
+
+/* COMM Commands between Driver to MPU */
+enum sphw_mgmt_cmd {
+	COMM_MGMT_CMD_FUNC_RESET = 0,
+	COMM_MGMT_CMD_FEATURE_NEGO,
+	COMM_MGMT_CMD_FLUSH_DOORBELL,
+	COMM_MGMT_CMD_START_FLUSH,
+	COMM_MGMT_CMD_SET_FUNC_FLR,
+	COMM_MGMT_CMD_GET_GLOBAL_ATTR,
+
+	COMM_MGMT_CMD_SET_CMDQ_CTXT = 20,
+	COMM_MGMT_CMD_SET_VAT,
+	COMM_MGMT_CMD_CFG_PAGESIZE,
+	COMM_MGMT_CMD_CFG_MSIX_CTRL_REG,
+	COMM_MGMT_CMD_SET_CEQ_CTRL_REG,
+	COMM_MGMT_CMD_SET_DMA_ATTR,
+
+	COMM_MGMT_CMD_GET_MQM_FIX_INFO = 40,
+	COMM_MGMT_CMD_SET_MQM_CFG_INFO,
+	COMM_MGMT_CMD_SET_MQM_SRCH_GPA,
+	COMM_MGMT_CMD_SET_PPF_TMR,
+	COMM_MGMT_CMD_SET_PPF_HT_GPA,
+	COMM_MGMT_CMD_SET_FUNC_TMR_BITMAT,
+
+	COMM_MGMT_CMD_GET_FW_VERSION = 60,
+	COMM_MGMT_CMD_GET_BOARD_INFO,
+	COMM_MGMT_CMD_SYNC_TIME,
+	COMM_MGMT_CMD_GET_HW_PF_INFOS,
+	COMM_MGMT_CMD_SEND_BDF_INFO,
+	COMM_MGMT_CMD_GET_VIRTIO_BDF_INFO,
+
+	COMM_MGMT_CMD_UPDATE_FW = 80,
+	COMM_MGMT_CMD_ACTIVE_FW,
+	COMM_MGMT_CMD_HOT_ACTIVE_FW,
+	COMM_MGMT_CMD_HOT_ACTIVE_DONE_NOTICE,
+	COMM_MGMT_CMD_SWITCH_CFG,
+	COMM_MGMT_CMD_CHECK_FLASH,
+	COMM_MGMT_CMD_CHECK_FLASH_RW,
+	COMM_MGMT_CMD_RESOURCE_CFG,
+
+	COMM_MGMT_CMD_FAULT_REPORT = 100,
+	COMM_MGMT_CMD_WATCHDOG_INFO,
+	COMM_MGMT_CMD_MGMT_RESET,
+	COMM_MGMT_CMD_FFM_SET,
+
+	COMM_MGMT_CMD_GET_LOG = 120,
+	COMM_MGMT_CMD_TEMP_OP,
+	COMM_MGMT_CMD_EN_AUTO_RST_CHIP,
+	COMM_MGMT_CMD_CFG_REG,
+	COMM_MGMT_CMD_GET_CHIP_ID,
+	COMM_MGMT_CMD_SYSINFO_DFX,
+	COMM_MGMT_CMD_PCIE_DFX_NTC,
+};
+
+#endif /* SPHW_COMMON_CMD_H */

drivers/net/ethernet/ramaxel/spnic/hw/sphw_comm_msg_intf.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#ifndef SPHW_COMM_MSG_INTF_H
+#define SPHW_COMM_MSG_INTF_H
+
+#include "sphw_mgmt_msg_base.h"
+
+#define FUNC_RESET_FLAG_MAX_VALUE ((1U << (RES_TYPE_IPSEC + 1)) - 1)
+struct comm_cmd_func_reset {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u16 rsvd1[3];
+	u64 reset_flag;
+};
+
+enum {
+	COMM_F_API_CHAIN = 1U << 0,
+};
+
+#define COMM_MAX_FEATURE_QWORD	4
+struct comm_cmd_feature_nego {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u8 opcode;	/* 1: set, 0: get */
+	u8 rsvd;
+	u64 s_feature[COMM_MAX_FEATURE_QWORD];
+};
+
+struct comm_cmd_clear_doorbell {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u16 rsvd1[3];
+};
+
+struct comm_cmd_clear_resource {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u16 rsvd1[3];
+};
+
+struct comm_global_attr {
+	u8 max_host_num;
+	u8 max_pf_num;
+	u16 vf_id_start;
+
+	u8 mgmt_host_node_id;	/* for api cmd to mgmt cpu */
+	u8 rsvd1[3];
+
+	u32 rsvd2[8];
+};
+
+struct comm_cmd_get_glb_attr {
+	struct mgmt_msg_head head;
+
+	struct comm_global_attr attr;
+};
+
+enum sphw_fw_ver_type {
+	SPHW_FW_VER_TYPE_BOOT,
+	SPHW_FW_VER_TYPE_MPU,
+	SPHW_FW_VER_TYPE_NPU,
+	SPHW_FW_VER_TYPE_SMU,
+	SPHW_FW_VER_TYPE_CFG,
+};
+
+#define SPHW_FW_VERSION_LEN		16
+#define SPHW_FW_COMPILE_TIME_LEN	20
+struct comm_cmd_get_fw_version {
+	struct mgmt_msg_head head;
+
+	u16 fw_type;
+	u16 rsvd1;
+	u8 ver[SPHW_FW_VERSION_LEN];
+	u8 time[SPHW_FW_COMPILE_TIME_LEN];
+};
+
+/* hardware define: cmdq context */
+struct cmdq_ctxt_info {
+	u64	curr_wqe_page_pfn;
+	u64	wq_block_pfn;
+};
+
+struct comm_cmd_cmdq_ctxt {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u8 cmdq_id;
+	u8 rsvd1[5];
+
+	struct cmdq_ctxt_info ctxt;
+};
+
+struct comm_cmd_root_ctxt {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u8 set_cmdq_depth;
+	u8 cmdq_depth;
+	u16 rx_buf_sz;
+	u8 lro_en;
+	u8 rsvd1;
+	u16 sq_depth;
+	u16 rq_depth;
+	u64 rsvd2;
+};
+
+struct comm_cmd_wq_page_size {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u8 opcode;
+	/* real_size=4KB*2^page_size, range(0~20) must be checked by driver */
+	u8 page_size;
+
+	u32 rsvd1;
+};
+
+struct comm_cmd_msix_config {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u8 opcode;
+	u8 rsvd1;
+	u16 msix_index;
+	u8 pending_cnt;
+	u8 coalesce_timer_cnt;
+	u8 resend_timer_cnt;
+	u8 lli_timer_cnt;
+	u8 lli_credit_cnt;
+	u8 rsvd2[5];
+};
+
+struct comm_cmd_dma_attr {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u8 entry_idx;
+	u8 st;
+	u8 at;
+	u8 ph;
+	u8 no_snooping;
+	u8 tph_en;
+	u32 resv1;
+};
+
+struct comm_cmd_ceq_ctrl_reg {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u16 q_id;
+	u32 ctrl0;
+	u32 ctrl1;
+	u32 rsvd1;
+};
+
+struct comm_cmd_func_tmr_bitmap_op {
+	struct mgmt_msg_head head;
+
+	u16 func_id;
+	u8 opcode; /* 1: start, 0: stop */
+	u8 rsvd1[5];
+};
+
+struct comm_cmd_ppf_tmr_op {
+	struct mgmt_msg_head head;
+
+	u8 ppf_id;
+	u8 opcode; /* 1: start, 0: stop */
+	u8 rsvd1[6];
+};
+
+struct comm_cmd_ht_gpa {
+	struct mgmt_msg_head head;
+
+	u8 host_id;
+	u32 rsvd1[7];
+	u64 page_pa0;
+	u64 page_pa1;
+};
+
+struct comm_cmd_get_eqm_num {
+	struct mgmt_msg_head head;
+
+	u8 host_id;
+	u8 rsvd1[3];
+	u32 chunk_num;
+	u32 search_gpa_num;
+};
+
+struct comm_cmd_eqm_cfg {
+	struct mgmt_msg_head head;
+
+	u8 host_id;
+	u8 valid;
+	u16 rsvd1;
+	u32 page_size;
+	u32 rsvd2;
+};
+
+struct comm_cmd_eqm_search_gpa {
+	struct mgmt_msg_head head;
+
+	u8 host_id;
+	u8 rsvd1[3];
+	u32 start_idx;
+	u32 num;
+	u32 rsvd2;
+	u64 gpa_hi52[0];
+};
+
+struct comm_cmd_ffm_info {
+	struct mgmt_msg_head head;
+
+	u8 node_id;
+	/* error level of the interrupt source */
+	u8 err_level;
+	/* Classification by interrupt source properties */
+	u16 err_type;
+	u32 err_csr_addr;
+	u32 err_csr_value;
+	u32 rsvd1;
+};
+
+struct sphw_board_info {
+	u8	board_type;
+	u8	port_num;
+	u8	port_speed;
+	u8	pcie_width;
+	u8	host_num;
+	u8	pf_num;
+	u16	vf_total_num;
+	u8	tile_num;
+	u8	qcm_num;
+	u8	core_num;
+	u8	work_mode;
+	u8	service_mode;
+	u8	pcie_mode;
+	u8	boot_sel;
+	u8	board_id;
+	u32	cfg_addr;
+};
+
+struct comm_cmd_board_info {
+	struct mgmt_msg_head head;
+
+	struct sphw_board_info info;
+	u32 rsvd[25];
+};
+
+struct comm_cmd_sync_time {
+	struct mgmt_msg_head head;
+
+	u64 mstime;
+	u64 rsvd1;
+};
+
+struct comm_cmd_bdf_info {
+	struct mgmt_msg_head head;
+
+	u16 function_idx;
+	u8 rsvd1[2];
+	u8 bus;
+	u8 device;
+	u8 function;
+	u8 rsvd2[5];
+};
+
+#endif

drivers/net/ethernet/ramaxel/spnic/hw/sphw_common.c

+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+
+#include "sphw_common.h"
+
+int sphw_dma_alloc_coherent_align(void *dev_hdl, u64 size, u64 align, unsigned int flag,
+				  struct sphw_dma_addr_align *mem_align)
+{
+	void *vaddr = NULL, *align_vaddr = NULL;
+	dma_addr_t paddr, align_paddr;
+	u64 real_size = size;
+
+	vaddr = dma_alloc_coherent(dev_hdl, real_size, &paddr, flag);
+	if (!vaddr)
+		return -ENOMEM;
+
+	align_paddr = ALIGN(paddr, align);
+	/* align */
+	if (align_paddr == paddr) {
+		align_vaddr = vaddr;
+		goto out;
+	}
+
+	dma_free_coherent(dev_hdl, real_size, vaddr, paddr);
+
+	/* realloc memory for align */
+	real_size = size + align;
+	vaddr = dma_alloc_coherent(dev_hdl, real_size, &paddr, flag);
+	if (!vaddr)
+		return -ENOMEM;
+
+	align_paddr = ALIGN(paddr, align);
+	align_vaddr = (void *)((u64)vaddr + (align_paddr - paddr));
+
+out:
+	mem_align->real_size = (u32)real_size;
+	mem_align->ori_vaddr = vaddr;
+	mem_align->ori_paddr = paddr;
+	mem_align->align_vaddr = align_vaddr;
+	mem_align->align_paddr = align_paddr;
+
+	return 0;
+}
+
+void sphw_dma_free_coherent_align(void *dev_hdl, struct sphw_dma_addr_align *mem_align)
+{
+	dma_free_coherent(dev_hdl, mem_align->real_size,
+			  mem_align->ori_vaddr, mem_align->ori_paddr);
+}
+
+int sphw_wait_for_timeout(void *priv_data, wait_cpl_handler handler,
+			  u32 wait_total_ms, u32 wait_once_us)
+{
+	enum sphw_wait_return ret;
+	unsigned long end;
+	/* Take 9/10 * wait_once_us as the minimum sleep time of usleep_range */
+	u32 usleep_min = wait_once_us - wait_once_us / 10;
+
+	if (!handler)
+		return -EINVAL;
+
+	end = jiffies + msecs_to_jiffies(wait_total_ms);
+	do {
+		ret = handler(priv_data);
+		if (ret == WAIT_PROCESS_CPL)
+			return 0;
+		else if (ret == WAIT_PROCESS_ERR)
+			return -EIO;
+
+		/* Sleep more than 20ms using msleep is accurate */
+		if (wait_once_us >= 20 * USEC_PER_MSEC)
+			msleep(wait_once_us / USEC_PER_MSEC);
+		else
+			usleep_range(usleep_min, wait_once_us);
+	} while (time_before(jiffies, end));
+
+	ret = handler(priv_data);
+	if (ret == WAIT_PROCESS_CPL)
+		return 0;
+	else if (ret == WAIT_PROCESS_ERR)
+		return -EIO;
+
+	return -ETIMEDOUT;
+}

drivers/net/ethernet/ramaxel/spnic/hw/sphw_common.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#ifndef SPHW_COMMON_H
+#define SPHW_COMMON_H
+
+#include <linux/types.h>
+
+struct sphw_dma_addr_align {
+	u32 real_size;
+
+	void *ori_vaddr;
+	dma_addr_t ori_paddr;
+
+	void *align_vaddr;
+	dma_addr_t align_paddr;
+};
+
+int sphw_dma_alloc_coherent_align(void *dev_hdl, u64 size, u64 align, unsigned int flag,
+				  struct sphw_dma_addr_align *mem_align);
+
+void sphw_dma_free_coherent_align(void *dev_hdl, struct sphw_dma_addr_align *mem_align);
+
+enum sphw_wait_return {
+	WAIT_PROCESS_CPL	= 0,
+	WAIT_PROCESS_WAITING	= 1,
+	WAIT_PROCESS_ERR	= 2,
+};
+
+typedef enum sphw_wait_return (*wait_cpl_handler)(void *priv_data);
+
+int sphw_wait_for_timeout(void *priv_data, wait_cpl_handler handler,
+			  u32 wait_total_ms, u32 wait_once_us);
+
+/* *
+ * sphw_cpu_to_be32 - convert data to big endian 32 bit format
+ * @data: the data to convert
+ * @len: length of data to convert, must be Multiple of 4B
+ */
+static inline void sphw_cpu_to_be32(void *data, int len)
+{
+	int i, chunk_sz = sizeof(u32);
+	u32 *mem = data;
+
+	if (!data)
+		return;
+
+	len = len / chunk_sz;
+
+	for (i = 0; i < len; i++) {
+		*mem = cpu_to_be32(*mem);
+		mem++;
+	}
+}
+
+/* *
+ * sphw_cpu_to_be32 - convert data from big endian 32 bit format
+ * @data: the data to convert
+ * @len: length of data to convert
+ */
+static inline void sphw_be32_to_cpu(void *data, int len)
+{
+	int i, chunk_sz = sizeof(u32);
+	u32 *mem = data;
+
+	if (!data)
+		return;
+
+	len = len / chunk_sz;
+
+	for (i = 0; i < len; i++) {
+		*mem = be32_to_cpu(*mem);
+		mem++;
+	}
+}
+
+struct sphw_sge {
+	u32 hi_addr;
+	u32 lo_addr;
+	u32 len;
+};
+
+/* *
+ * sphw_set_sge - set dma area in scatter gather entry
+ * @sge: scatter gather entry
+ * @addr: dma address
+ * @len: length of relevant data in the dma address
+ */
+static inline void sphw_set_sge(struct sphw_sge *sge, dma_addr_t addr, int len)
+{
+	sge->hi_addr = upper_32_bits(addr);
+	sge->lo_addr = lower_32_bits(addr);
+	sge->len = len;
+}
+
+#define sphw_hw_be32(val) (val)
+#define sphw_hw_cpu32(val) (val)
+#define sphw_hw_cpu16(val) (val)
+
+static inline void sphw_hw_be32_len(void *data, int len)
+{
+}
+
+static inline void sphw_hw_cpu32_len(void *data, int len)
+{
+}
+
+#define sdk_err(dev, format, ...) dev_err(dev, "[COMM]" format, ##__VA_ARGS__)
+#define sdk_warn(dev, format, ...) dev_warn(dev, "[COMM]" format, ##__VA_ARGS__)
+#define sdk_notice(dev, format, ...) dev_notice(dev, "[COMM]" format, ##__VA_ARGS__)
+#define sdk_info(dev, format, ...) dev_info(dev, "[COMM]" format, ##__VA_ARGS__)
+
+#define nic_err(dev, format, ...) dev_err(dev, "[NIC]" format, ##__VA_ARGS__)
+#define nic_warn(dev, format, ...) dev_warn(dev, "[NIC]" format, ##__VA_ARGS__)
+#define nic_notice(dev, format, ...) dev_notice(dev, "[NIC]" format, ##__VA_ARGS__)
+#define nic_info(dev, format, ...) dev_info(dev, "[NIC]" format, ##__VA_ARGS__)
+
+#endif

drivers/net/ethernet/ramaxel/spnic/hw/sphw_mgmt_msg_base.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */
+
+#ifndef SPHW_MGMT_MSG_BASE_H
+#define SPHW_MGMT_MSG_BASE_H
+
+#define MGMT_MSG_CMD_OP_SET	1
+#define MGMT_MSG_CMD_OP_GET	0
+
+#define MGMT_MSG_CMD_OP_START	1
+#define MGMT_MSG_CMD_OP_STOP	0
+
+struct mgmt_msg_head {
+	u8 status;
+	u8 version;
+	u8 rsvd0[6];
+};
+
+#endif