pinctrl: microchip-sgpio: Fix wrong register offset for IRQ trigger

This patch fixes using a wrong register offset when configuring an IRQ
trigger type.

Fixes: be2dc859 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)")
Reported-by: NGustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: NLars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: NGustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/20210203123825.611576-1-lars.povlsen@microchip.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

drivers/pinctrl/pinctrl-microchip-sgpio.c

@@ -572,7 +572,7 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,
 	/* Type value spread over 2 registers sets: low, high bit */
 	sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
 			 BIT(addr.port), (!!(type & 0x1)) << addr.port);
-	sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit,
+	sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
 			 BIT(addr.port), (!!(type & 0x2)) << addr.port);
 
 	if (type == SGPIO_INT_TRG_LEVEL)