drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
This patch defines register definitions required for ICL voltage vswing programming for Combo PHY DDI Ports. It uses the same bit definitions and macros as the CNL voltage swing sequences. v8 (from Paulo): * Rebase. v7: * Kill _MMIIO_PORT2_LN (Paulo) v6: * Replace some spaces with TAB (Paulo) v5: * Use _PORT instead of _PICK (Paulo) * Remove DW7 defs for ICL, not used (Paulo) v4: * Rebase after _PICK was used instead of _PORT3 * Use _PICK for _MMIO_PORT2 since address of B is less than address of A so cant use the math (Paulo) v3: * Make changes to the existing macro in a diff patch (Paulo) v2: * Add new defs fro ICL regs (Paulo) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NManasi Navare <manasi.d.navare@intel.com> Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180323172419.24911-2-paulo.r.zanoni@intel.com
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