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提交 58d08319 编写于 作者: J Jesper Nilsson 提交者： Jesper Nilsson
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CRIS v32: Add hardware dependent include files and defconfigs for ETRAX FS and ARTPEC-3 chips. 

The header files describe the hardware registers available in both
these chips, note that most of this documentation is automatically
generated from the hardware implementation.
上级 035e111f
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Showing with 19631 addition and 0 deletion
arch/cris/artpec_3_defconfig 0 → 100644
浏览文件 @ 58d08319
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.24-rc3
# Mon Dec 3 11:18:54 2007
#
CONFIG_MMU=y
CONFIG_ZONE_DMA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_IOMAP=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NO_IOPORT=y
CONFIG_NO_IOMEM=y
CONFIG_FORCE_MAX_ZONEORDER=6
CONFIG_CRIS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
#
# General setup
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
# CONFIG_ETRAX_WATCHDOG is not set
CONFIG_ETRAX_FAST_TIMER=y
# CONFIG_ETRAX_KMALLOCED_MODULES is not set
# CONFIG_OOM_REBOOT is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
#
# Hardware setup
#
# CONFIG_ETRAX100LX is not set
# CONFIG_ETRAX100LX_V2 is not set
# CONFIG_SVINTO_SIM is not set
# CONFIG_ETRAXFS is not set
CONFIG_CRIS_MACH_ARTPEC3=y
# CONFIG_ETRAX_VCS_SIM is not set
# CONFIG_ETRAX_ARCH_V10 is not set
CONFIG_ETRAX_ARCH_V32=y
CONFIG_ETRAX_DRAM_SIZE=32
CONFIG_ETRAX_VMEM_SIZE=8
CONFIG_ETRAX_FLASH_BUSWIDTH=2
CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
CONFIG_ETRAX_FLASH1_SIZE=4
CONFIG_ETRAX_DEBUG_PORT0=y
# CONFIG_ETRAX_DEBUG_PORT1 is not set
# CONFIG_ETRAX_DEBUG_PORT2 is not set
# CONFIG_ETRAX_DEBUG_PORT3 is not set
# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
CONFIG_ETRAX_SERIAL_PORTS=5
CONFIG_ETRAX_DEF_GIO_PA_OE=1c
CONFIG_ETRAX_DEF_GIO_PA_OUT=00
CONFIG_ETRAX_DEF_GIO_PB_OE=00000
CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
CONFIG_ETRAX_DEF_GIO_PC_OE=00000
CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
#
# Artpec-3 options
#
CONFIG_ETRAX_L2CACHE=y
CONFIG_ETRAX_DDR=y
CONFIG_ETRAX_DDR2_MRS=0
CONFIG_ETRAX_DDR2_TIMING=0
CONFIG_ETRAX_DDR2_CONFIG=0
CONFIG_ETRAX_PIO_CE0_CFG=0
CONFIG_ETRAX_PIO_CE1_CFG=0
CONFIG_ETRAX_PIO_CE2_CFG=0
# CONFIG_CPU_FREQ is not set
# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
CONFIG_ETRAX_NBR_LED_GRP_ONE=y
# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
CONFIG_ETRAX_LED_G_NET0="PA3"
CONFIG_ETRAX_LED_R_NET0="PA4"
CONFIG_ETRAX_V32_LED2G="PA5"
CONFIG_ETRAX_V32_LED2R="PA6"
CONFIG_ETRAX_V32_LED3G="PA7"
CONFIG_ETRAX_V32_LED3R="PA7"
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IP_VS is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
#
# Core Netfilter Configuration
#
# CONFIG_NETFILTER_NETLINK is not set
# CONFIG_NF_CONNTRACK_ENABLED is not set
# CONFIG_NF_CONNTRACK is not set
# CONFIG_NETFILTER_XTABLES is not set
#
# IP: Netfilter Configuration
#
# CONFIG_IP_NF_QUEUE is not set
# CONFIG_IP_NF_IPTABLES is not set
# CONFIG_IP_NF_ARPTABLES is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Drivers for built-in interfaces
#
CONFIG_ETRAX_ETHERNET=y
# CONFIG_ETRAX_IDE is not set
CONFIG_ETRAX_AXISFLASHMAP=y
CONFIG_ETRAX_PTABLE_SECTOR=65536
# CONFIG_ETRAX_I2C is not set
# CONFIG_ETRAX_GPIO is not set
# CONFIG_ETRAX_NO_PHY is not set
# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
# CONFIG_ETRAX_ETHERNET_GBIT is not set
# CONFIG_ETRAXFS_SERIAL is not set
# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
# CONFIG_ETRAX_NANDFLASH is not set
# CONFIG_ETRAX_CARDBUS is not set
# CONFIG_ETRAX_IOP_FW_LOAD is not set
# CONFIG_ETRAX_STREAMCOPROC is not set
# CONFIG_ETRAX_SPI_MMC is not set
# CONFIG_ETRAX_SPI_MMC_BOARD is not set
# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_RTC_CLASS is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_HW_RANDOM=y
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PROFILING is not set
# CONFIG_SYSTEM_PROFILER is not set
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SAMPLES is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_DMA=y
arch/cris/etraxfs_defconfig 0 → 100644
浏览文件 @ 58d08319
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.24-rc3
# Fri Nov 30 14:24:26 2007
#
CONFIG_MMU=y
CONFIG_ZONE_DMA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_IOMAP=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NO_IOPORT=y
CONFIG_NO_IOMEM=y
CONFIG_FORCE_MAX_ZONEORDER=6
CONFIG_CRIS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
#
# General setup
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
# CONFIG_ETRAX_WATCHDOG is not set
CONFIG_ETRAX_FAST_TIMER=y
# CONFIG_ETRAX_KMALLOCED_MODULES is not set
# CONFIG_OOM_REBOOT is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
#
# Hardware setup
#
# CONFIG_ETRAX100LX is not set
# CONFIG_ETRAX100LX_V2 is not set
# CONFIG_SVINTO_SIM is not set
CONFIG_ETRAXFS=y
# CONFIG_CRIS_MACH_ARTPEC3 is not set
# CONFIG_ETRAX_VCS_SIM is not set
# CONFIG_ETRAX_ARCH_V10 is not set
CONFIG_ETRAX_ARCH_V32=y
CONFIG_ETRAX_DRAM_SIZE=32
CONFIG_ETRAX_FLASH_BUSWIDTH=2
CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
CONFIG_ETRAX_FLASH1_SIZE=4
CONFIG_ETRAX_DEBUG_PORT0=y
# CONFIG_ETRAX_DEBUG_PORT1 is not set
# CONFIG_ETRAX_DEBUG_PORT2 is not set
# CONFIG_ETRAX_DEBUG_PORT3 is not set
# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
#
# ETRAX FS options
#
CONFIG_ETRAX_SERIAL_PORTS=4
CONFIG_ETRAX_MEM_GRP1_CONFIG=4044a
CONFIG_ETRAX_MEM_GRP2_CONFIG=0
CONFIG_ETRAX_MEM_GRP3_CONFIG=0
CONFIG_ETRAX_MEM_GRP4_CONFIG=0
CONFIG_ETRAX_SDRAM_GRP0_CONFIG=336
CONFIG_ETRAX_SDRAM_GRP1_CONFIG=0
CONFIG_ETRAX_SDRAM_TIMING=104a
CONFIG_ETRAX_SDRAM_COMMAND=0
CONFIG_ETRAX_DEF_GIO_PA_OE=1c
CONFIG_ETRAX_DEF_GIO_PA_OUT=00
CONFIG_ETRAX_DEF_GIO_PB_OE=00000
CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
CONFIG_ETRAX_DEF_GIO_PC_OE=00000
CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
CONFIG_ETRAX_DEF_GIO_PD_OE=00000
CONFIG_ETRAX_DEF_GIO_PD_OUT=00000
CONFIG_ETRAX_DEF_GIO_PE_OE=00000
CONFIG_ETRAX_DEF_GIO_PE_OUT=00000
# CONFIG_CPU_FREQ is not set
# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
CONFIG_ETRAX_NBR_LED_GRP_ONE=y
# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
CONFIG_ETRAX_LED_G_NET0="PA3"
CONFIG_ETRAX_LED_R_NET0="PA4"
CONFIG_ETRAX_V32_LED2G="PA5"
CONFIG_ETRAX_V32_LED2R="PA6"
CONFIG_ETRAX_V32_LED3G="PA7"
CONFIG_ETRAX_V32_LED3R="PA7"
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IP_VS is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
#
# Core Netfilter Configuration
#
# CONFIG_NETFILTER_NETLINK is not set
# CONFIG_NF_CONNTRACK_ENABLED is not set
# CONFIG_NF_CONNTRACK is not set
# CONFIG_NETFILTER_XTABLES is not set
#
# IP: Netfilter Configuration
#
# CONFIG_IP_NF_QUEUE is not set
# CONFIG_IP_NF_IPTABLES is not set
# CONFIG_IP_NF_ARPTABLES is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Drivers for built-in interfaces
#
CONFIG_ETRAX_ETHERNET=y
# CONFIG_ETRAX_IDE is not set
CONFIG_ETRAX_AXISFLASHMAP=y
CONFIG_ETRAX_PTABLE_SECTOR=65536
# CONFIG_ETRAX_I2C is not set
# CONFIG_ETRAX_GPIO is not set
# CONFIG_ETRAX_NO_PHY is not set
# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
# CONFIG_ETRAX_ETHERNET_IFACE1 is not set
# CONFIG_ETRAXFS_SERIAL is not set
# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
# CONFIG_ETRAX_NANDFLASH is not set
# CONFIG_ETRAX_CARDBUS is not set
# CONFIG_ETRAX_IOP_FW_LOAD is not set
# CONFIG_ETRAX_STREAMCOPROC is not set
# CONFIG_ETRAX_SPI_MMC is not set
# CONFIG_ETRAX_SPI_MMC_BOARD is not set
# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_RTC_CLASS is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_HW_RANDOM=y
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PROFILING is not set
# CONFIG_SYSTEM_PROFILER is not set
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SAMPLES is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_DMA=y
include/asm-cris/arch-v32/mach-a3/arbiter.h 0 → 100644
浏览文件 @ 58d08319
#ifndef _ASM_CRIS_ARCH_ARBITER_H
#define _ASM_CRIS_ARCH_ARBITER_H
#define EXT_REGION 0
#define INT_REGION 1
typedef void (watch_callback)(void);
enum {
arbiter_all_dmas = 0x7fe,
arbiter_cpu = 0x1800,
arbiter_all_clients = 0x7fff
};
enum {
arbiter_bar_all_clients = 0x1ff
};
enum {
arbiter_all_read = 0x55,
arbiter_all_write = 0xaa,
arbiter_all_accesses = 0xff
};
#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
int crisv32_arbiter_allocate_bandwith(int client, int region,
unsigned long bandwidth);
int crisv32_arbiter_watch(unsigned long start, unsigned long size,
unsigned long clients, unsigned long accesses,
watch_callback * cb);
int crisv32_arbiter_unwatch(int id);
#endif
include/asm-cris/arch-v32/mach-a3/dma.h 0 → 100644
浏览文件 @ 58d08319
#ifndef _ASM_ARCH_CRIS_DMA_H
#define _ASM_ARCH_CRIS_DMA_H
/* Defines for using and allocating dma channels. */
#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
enum dma_owner {
dma_eth,
dma_ser0,
dma_ser1,
dma_ser2,
dma_ser3,
dma_ser4,
dma_iop,
dma_sser,
dma_strp,
dma_h264,
dma_jpeg
};
int crisv32_request_dma(unsigned int dmanr, const char *device_id,
unsigned options, unsigned bandwidth, enum dma_owner owner);
void crisv32_free_dma(unsigned int dmanr);
/* Masks used by crisv32_request_dma options: */
#define DMA_VERBOSE_ON_ERROR 1
#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
#define DMA_INT_MEM 4
#endif /* _ASM_ARCH_CRIS_DMA_H */
include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __clkgen_defs_asm_h
#define __clkgen_defs_asm_h
/*
* This file is autogenerated from
* file: clkgen.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_bootsel, scope clkgen, type r */
#define reg_clkgen_r_bootsel___boot_mode___lsb 0
#define reg_clkgen_r_bootsel___boot_mode___width 5
#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
#define reg_clkgen_r_bootsel___intern_main_clk___width 1
#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
#define reg_clkgen_r_bootsel_offset 0
/* Register rw_clk_ctrl, scope clkgen, type rw */
#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
#define reg_clkgen_rw_clk_ctrl___pll___width 1
#define reg_clkgen_rw_clk_ctrl___pll___bit 0
#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
#define reg_clkgen_rw_clk_ctrl___cpu___width 1
#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
#define reg_clkgen_rw_clk_ctrl___vin___width 1
#define reg_clkgen_rw_clk_ctrl___vin___bit 3
#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
#define reg_clkgen_rw_clk_ctrl___sclr___width 1
#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
#define reg_clkgen_rw_clk_ctrl___h264___width 1
#define reg_clkgen_rw_clk_ctrl___h264___bit 5
#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
#define reg_clkgen_rw_clk_ctrl___eth___width 1
#define reg_clkgen_rw_clk_ctrl___eth___bit 8
#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
#define reg_clkgen_rw_clk_ctrl_offset 4
/* Constants */
#define regk_clkgen_eth1000_rx 0x0000000c
#define regk_clkgen_eth1000_tx 0x0000000e
#define regk_clkgen_eth100_rx 0x0000001d
#define regk_clkgen_eth100_rx_half 0x0000001c
#define regk_clkgen_eth100_tx 0x0000001f
#define regk_clkgen_eth100_tx_half 0x0000001e
#define regk_clkgen_nand_3_2 0x00000000
#define regk_clkgen_nand_3_2_0x30 0x00000002
#define regk_clkgen_nand_3_2_0x30_pll 0x00000012
#define regk_clkgen_nand_3_2_pll 0x00000010
#define regk_clkgen_nand_3_3 0x00000001
#define regk_clkgen_nand_3_3_0x30 0x00000003
#define regk_clkgen_nand_3_3_0x30_pll 0x00000013
#define regk_clkgen_nand_3_3_pll 0x00000011
#define regk_clkgen_nand_4_2 0x00000004
#define regk_clkgen_nand_4_2_0x30 0x00000006
#define regk_clkgen_nand_4_2_0x30_pll 0x00000016
#define regk_clkgen_nand_4_2_pll 0x00000014
#define regk_clkgen_nand_4_3 0x00000005
#define regk_clkgen_nand_4_3_0x30 0x00000007
#define regk_clkgen_nand_4_3_0x30_pll 0x00000017
#define regk_clkgen_nand_4_3_pll 0x00000015
#define regk_clkgen_nand_5_2 0x00000008
#define regk_clkgen_nand_5_2_0x30 0x0000000a
#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a
#define regk_clkgen_nand_5_2_pll 0x00000018
#define regk_clkgen_nand_5_3 0x00000009
#define regk_clkgen_nand_5_3_0x30 0x0000000b
#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b
#define regk_clkgen_nand_5_3_pll 0x00000019
#define regk_clkgen_no 0x00000000
#define regk_clkgen_rw_clk_ctrl_default 0x00000002
#define regk_clkgen_ser 0x0000000d
#define regk_clkgen_ser_pll 0x0000000f
#define regk_clkgen_yes 0x00000001
#endif /* __clkgen_defs_asm_h */
include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __ddr2_defs_asm_h
#define __ddr2_defs_asm_h
/*
* This file is autogenerated from
* file: ddr2.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope ddr2, type rw */
#define reg_ddr2_rw_cfg___col_width___lsb 0
#define reg_ddr2_rw_cfg___col_width___width 4
#define reg_ddr2_rw_cfg___nr_banks___lsb 4
#define reg_ddr2_rw_cfg___nr_banks___width 1
#define reg_ddr2_rw_cfg___nr_banks___bit 4
#define reg_ddr2_rw_cfg___bw___lsb 5
#define reg_ddr2_rw_cfg___bw___width 1
#define reg_ddr2_rw_cfg___bw___bit 5
#define reg_ddr2_rw_cfg___nr_ref___lsb 6
#define reg_ddr2_rw_cfg___nr_ref___width 4
#define reg_ddr2_rw_cfg___ref_interval___lsb 10
#define reg_ddr2_rw_cfg___ref_interval___width 11
#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
#define reg_ddr2_rw_cfg___odt_ctrl___width 2
#define reg_ddr2_rw_cfg___odt_mem___lsb 23
#define reg_ddr2_rw_cfg___odt_mem___width 1
#define reg_ddr2_rw_cfg___odt_mem___bit 23
#define reg_ddr2_rw_cfg___imp_strength___lsb 24
#define reg_ddr2_rw_cfg___imp_strength___width 1
#define reg_ddr2_rw_cfg___imp_strength___bit 24
#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
#define reg_ddr2_rw_cfg___imp_cal_override___width 1
#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
#define reg_ddr2_rw_cfg___dll_override___lsb 27
#define reg_ddr2_rw_cfg___dll_override___width 1
#define reg_ddr2_rw_cfg___dll_override___bit 27
#define reg_ddr2_rw_cfg_offset 0
/* Register rw_timing, scope ddr2, type rw */
#define reg_ddr2_rw_timing___wr___lsb 0
#define reg_ddr2_rw_timing___wr___width 3
#define reg_ddr2_rw_timing___rcd___lsb 3
#define reg_ddr2_rw_timing___rcd___width 3
#define reg_ddr2_rw_timing___rp___lsb 6
#define reg_ddr2_rw_timing___rp___width 3
#define reg_ddr2_rw_timing___ras___lsb 9
#define reg_ddr2_rw_timing___ras___width 4
#define reg_ddr2_rw_timing___rfc___lsb 13
#define reg_ddr2_rw_timing___rfc___width 7
#define reg_ddr2_rw_timing___rc___lsb 20
#define reg_ddr2_rw_timing___rc___width 5
#define reg_ddr2_rw_timing___rtp___lsb 25
#define reg_ddr2_rw_timing___rtp___width 2
#define reg_ddr2_rw_timing___rtw___lsb 27
#define reg_ddr2_rw_timing___rtw___width 3
#define reg_ddr2_rw_timing___wtr___lsb 30
#define reg_ddr2_rw_timing___wtr___width 2
#define reg_ddr2_rw_timing_offset 4
/* Register rw_latency, scope ddr2, type rw */
#define reg_ddr2_rw_latency___cas___lsb 0
#define reg_ddr2_rw_latency___cas___width 3
#define reg_ddr2_rw_latency___additive___lsb 3
#define reg_ddr2_rw_latency___additive___width 3
#define reg_ddr2_rw_latency_offset 8
/* Register rw_phy_cfg, scope ddr2, type rw */
#define reg_ddr2_rw_phy_cfg___en___lsb 0
#define reg_ddr2_rw_phy_cfg___en___width 1
#define reg_ddr2_rw_phy_cfg___en___bit 0
#define reg_ddr2_rw_phy_cfg_offset 12
/* Register rw_phy_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
#define reg_ddr2_rw_phy_ctrl___rst___width 1
#define reg_ddr2_rw_phy_ctrl___rst___bit 0
#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
#define reg_ddr2_rw_phy_ctrl_offset 16
/* Register rw_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
#define reg_ddr2_rw_ctrl___mrs_data___width 16
#define reg_ddr2_rw_ctrl___cmd___lsb 16
#define reg_ddr2_rw_ctrl___cmd___width 8
#define reg_ddr2_rw_ctrl_offset 20
/* Register rw_pwr_down, scope ddr2, type rw */
#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
#define reg_ddr2_rw_pwr_down___self_ref___width 2
#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
#define reg_ddr2_rw_pwr_down___phy_en___width 1
#define reg_ddr2_rw_pwr_down___phy_en___bit 2
#define reg_ddr2_rw_pwr_down_offset 24
/* Register r_stat, scope ddr2, type r */
#define reg_ddr2_r_stat___dll_lock___lsb 0
#define reg_ddr2_r_stat___dll_lock___width 1
#define reg_ddr2_r_stat___dll_lock___bit 0
#define reg_ddr2_r_stat___dll_delay_code___lsb 1
#define reg_ddr2_r_stat___dll_delay_code___width 7
#define reg_ddr2_r_stat___imp_cal_done___lsb 8
#define reg_ddr2_r_stat___imp_cal_done___width 1
#define reg_ddr2_r_stat___imp_cal_done___bit 8
#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
#define reg_ddr2_r_stat___imp_cal_fault___width 1
#define reg_ddr2_r_stat___imp_cal_fault___bit 9
#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
#define reg_ddr2_r_stat___cal_imp_pu___width 4
#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
#define reg_ddr2_r_stat___cal_imp_pd___width 4
#define reg_ddr2_r_stat_offset 28
/* Register rw_imp_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
#define reg_ddr2_rw_imp_ctrl_offset 32
#define STRIDE_ddr2_rw_dll_ctrl 4
/* Register rw_dll_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
#define reg_ddr2_rw_dll_ctrl___mode___width 1
#define reg_ddr2_rw_dll_ctrl___mode___bit 0
#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
#define reg_ddr2_rw_dll_ctrl_offset 36
#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
/* Constants */
#define regk_ddr2_al0 0x00000000
#define regk_ddr2_al1 0x00000008
#define regk_ddr2_al2 0x00000010
#define regk_ddr2_al3 0x00000018
#define regk_ddr2_al4 0x00000020
#define regk_ddr2_auto 0x00000003
#define regk_ddr2_bank4 0x00000000
#define regk_ddr2_bank8 0x00000001
#define regk_ddr2_bl4 0x00000002
#define regk_ddr2_bl8 0x00000003
#define regk_ddr2_bt_il 0x00000008
#define regk_ddr2_bt_seq 0x00000000
#define regk_ddr2_bw16 0x00000001
#define regk_ddr2_bw32 0x00000000
#define regk_ddr2_cas2 0x00000020
#define regk_ddr2_cas3 0x00000030
#define regk_ddr2_cas4 0x00000040
#define regk_ddr2_cas5 0x00000050
#define regk_ddr2_deselect 0x000000c0
#define regk_ddr2_dic_weak 0x00000002
#define regk_ddr2_direct 0x00000001
#define regk_ddr2_dis 0x00000000
#define regk_ddr2_dll_dis 0x00000001
#define regk_ddr2_dll_en 0x00000000
#define regk_ddr2_dll_rst 0x00000100
#define regk_ddr2_emrs 0x00000081
#define regk_ddr2_emrs2 0x00000082
#define regk_ddr2_emrs3 0x00000083
#define regk_ddr2_full 0x00000001
#define regk_ddr2_hi_ref_rate 0x00000080
#define regk_ddr2_mrs 0x00000080
#define regk_ddr2_no 0x00000000
#define regk_ddr2_nop 0x000000b8
#define regk_ddr2_ocd_adj 0x00000200
#define regk_ddr2_ocd_default 0x00000380
#define regk_ddr2_ocd_drive0 0x00000100
#define regk_ddr2_ocd_drive1 0x00000080
#define regk_ddr2_ocd_exit 0x00000000
#define regk_ddr2_odt_dis 0x00000000
#define regk_ddr2_offs 0x00000000
#define regk_ddr2_pre 0x00000090
#define regk_ddr2_pre_all 0x00000400
#define regk_ddr2_pwr_down_fast 0x00000000
#define regk_ddr2_pwr_down_slow 0x00001000
#define regk_ddr2_ref 0x00000088
#define regk_ddr2_rtt150 0x00000040
#define regk_ddr2_rtt50 0x00000044
#define regk_ddr2_rtt75 0x00000004
#define regk_ddr2_rw_cfg_default 0x00186000
#define regk_ddr2_rw_dll_ctrl_default 0x00000000
#define regk_ddr2_rw_dll_ctrl_size 0x00000004
#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000
#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004
#define regk_ddr2_rw_latency_default 0x00000000
#define regk_ddr2_rw_phy_cfg_default 0x00000000
#define regk_ddr2_rw_pwr_down_default 0x00000000
#define regk_ddr2_rw_timing_default 0x00000000
#define regk_ddr2_s1Gb 0x0000001a
#define regk_ddr2_s256Mb 0x0000000f
#define regk_ddr2_s2Gb 0x00000027
#define regk_ddr2_s4Gb 0x00000042
#define regk_ddr2_s512Mb 0x00000015
#define regk_ddr2_temp0_85 0x00000618
#define regk_ddr2_temp85_95 0x0000030c
#define regk_ddr2_term150 0x00000002
#define regk_ddr2_term50 0x00000003
#define regk_ddr2_term75 0x00000001
#define regk_ddr2_test 0x00000080
#define regk_ddr2_weak 0x00000000
#define regk_ddr2_wr2 0x00000200
#define regk_ddr2_wr3 0x00000400
#define regk_ddr2_yes 0x00000001
#endif /* __ddr2_defs_asm_h */
include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __pio_defs_asm_h
#define __pio_defs_asm_h
/*
* This file is autogenerated from
* file: pio.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_data, scope pio, type rw */
#define reg_pio_rw_data_offset 64
/* Register rw_io_access0, scope pio, type rw */
#define reg_pio_rw_io_access0___data___lsb 0
#define reg_pio_rw_io_access0___data___width 8
#define reg_pio_rw_io_access0_offset 0
/* Register rw_io_access1, scope pio, type rw */
#define reg_pio_rw_io_access1___data___lsb 0
#define reg_pio_rw_io_access1___data___width 8
#define reg_pio_rw_io_access1_offset 4
/* Register rw_io_access2, scope pio, type rw */
#define reg_pio_rw_io_access2___data___lsb 0
#define reg_pio_rw_io_access2___data___width 8
#define reg_pio_rw_io_access2_offset 8
/* Register rw_io_access3, scope pio, type rw */
#define reg_pio_rw_io_access3___data___lsb 0
#define reg_pio_rw_io_access3___data___width 8
#define reg_pio_rw_io_access3_offset 12
/* Register rw_io_access4, scope pio, type rw */
#define reg_pio_rw_io_access4___data___lsb 0
#define reg_pio_rw_io_access4___data___width 8
#define reg_pio_rw_io_access4_offset 16
/* Register rw_io_access5, scope pio, type rw */
#define reg_pio_rw_io_access5___data___lsb 0
#define reg_pio_rw_io_access5___data___width 8
#define reg_pio_rw_io_access5_offset 20
/* Register rw_io_access6, scope pio, type rw */
#define reg_pio_rw_io_access6___data___lsb 0
#define reg_pio_rw_io_access6___data___width 8
#define reg_pio_rw_io_access6_offset 24
/* Register rw_io_access7, scope pio, type rw */
#define reg_pio_rw_io_access7___data___lsb 0
#define reg_pio_rw_io_access7___data___width 8
#define reg_pio_rw_io_access7_offset 28
/* Register rw_io_access8, scope pio, type rw */
#define reg_pio_rw_io_access8___data___lsb 0
#define reg_pio_rw_io_access8___data___width 8
#define reg_pio_rw_io_access8_offset 32
/* Register rw_io_access9, scope pio, type rw */
#define reg_pio_rw_io_access9___data___lsb 0
#define reg_pio_rw_io_access9___data___width 8
#define reg_pio_rw_io_access9_offset 36
/* Register rw_io_access10, scope pio, type rw */
#define reg_pio_rw_io_access10___data___lsb 0
#define reg_pio_rw_io_access10___data___width 8
#define reg_pio_rw_io_access10_offset 40
/* Register rw_io_access11, scope pio, type rw */
#define reg_pio_rw_io_access11___data___lsb 0
#define reg_pio_rw_io_access11___data___width 8
#define reg_pio_rw_io_access11_offset 44
/* Register rw_io_access12, scope pio, type rw */
#define reg_pio_rw_io_access12___data___lsb 0
#define reg_pio_rw_io_access12___data___width 8
#define reg_pio_rw_io_access12_offset 48
/* Register rw_io_access13, scope pio, type rw */
#define reg_pio_rw_io_access13___data___lsb 0
#define reg_pio_rw_io_access13___data___width 8
#define reg_pio_rw_io_access13_offset 52
/* Register rw_io_access14, scope pio, type rw */
#define reg_pio_rw_io_access14___data___lsb 0
#define reg_pio_rw_io_access14___data___width 8
#define reg_pio_rw_io_access14_offset 56
/* Register rw_io_access15, scope pio, type rw */
#define reg_pio_rw_io_access15___data___lsb 0
#define reg_pio_rw_io_access15___data___width 8
#define reg_pio_rw_io_access15_offset 60
/* Register rw_ce0_cfg, scope pio, type rw */
#define reg_pio_rw_ce0_cfg___lw___lsb 0
#define reg_pio_rw_ce0_cfg___lw___width 6
#define reg_pio_rw_ce0_cfg___ew___lsb 6
#define reg_pio_rw_ce0_cfg___ew___width 3
#define reg_pio_rw_ce0_cfg___zw___lsb 9
#define reg_pio_rw_ce0_cfg___zw___width 3
#define reg_pio_rw_ce0_cfg___aw___lsb 12
#define reg_pio_rw_ce0_cfg___aw___width 2
#define reg_pio_rw_ce0_cfg___mode___lsb 14
#define reg_pio_rw_ce0_cfg___mode___width 2
#define reg_pio_rw_ce0_cfg_offset 68
/* Register rw_ce1_cfg, scope pio, type rw */
#define reg_pio_rw_ce1_cfg___lw___lsb 0
#define reg_pio_rw_ce1_cfg___lw___width 6
#define reg_pio_rw_ce1_cfg___ew___lsb 6
#define reg_pio_rw_ce1_cfg___ew___width 3
#define reg_pio_rw_ce1_cfg___zw___lsb 9
#define reg_pio_rw_ce1_cfg___zw___width 3
#define reg_pio_rw_ce1_cfg___aw___lsb 12
#define reg_pio_rw_ce1_cfg___aw___width 2
#define reg_pio_rw_ce1_cfg___mode___lsb 14
#define reg_pio_rw_ce1_cfg___mode___width 2
#define reg_pio_rw_ce1_cfg_offset 72
/* Register rw_ce2_cfg, scope pio, type rw */
#define reg_pio_rw_ce2_cfg___lw___lsb 0
#define reg_pio_rw_ce2_cfg___lw___width 6
#define reg_pio_rw_ce2_cfg___ew___lsb 6
#define reg_pio_rw_ce2_cfg___ew___width 3
#define reg_pio_rw_ce2_cfg___zw___lsb 9
#define reg_pio_rw_ce2_cfg___zw___width 3
#define reg_pio_rw_ce2_cfg___aw___lsb 12
#define reg_pio_rw_ce2_cfg___aw___width 2
#define reg_pio_rw_ce2_cfg___mode___lsb 14
#define reg_pio_rw_ce2_cfg___mode___width 2
#define reg_pio_rw_ce2_cfg_offset 76
/* Register rw_dout, scope pio, type rw */
#define reg_pio_rw_dout___data___lsb 0
#define reg_pio_rw_dout___data___width 8
#define reg_pio_rw_dout___rd_n___lsb 8
#define reg_pio_rw_dout___rd_n___width 1
#define reg_pio_rw_dout___rd_n___bit 8
#define reg_pio_rw_dout___wr_n___lsb 9
#define reg_pio_rw_dout___wr_n___width 1
#define reg_pio_rw_dout___wr_n___bit 9
#define reg_pio_rw_dout___a0___lsb 10
#define reg_pio_rw_dout___a0___width 1
#define reg_pio_rw_dout___a0___bit 10
#define reg_pio_rw_dout___a1___lsb 11
#define reg_pio_rw_dout___a1___width 1
#define reg_pio_rw_dout___a1___bit 11
#define reg_pio_rw_dout___ce0_n___lsb 12
#define reg_pio_rw_dout___ce0_n___width 1
#define reg_pio_rw_dout___ce0_n___bit 12
#define reg_pio_rw_dout___ce1_n___lsb 13
#define reg_pio_rw_dout___ce1_n___width 1
#define reg_pio_rw_dout___ce1_n___bit 13
#define reg_pio_rw_dout___ce2_n___lsb 14
#define reg_pio_rw_dout___ce2_n___width 1
#define reg_pio_rw_dout___ce2_n___bit 14
#define reg_pio_rw_dout___rdy___lsb 15
#define reg_pio_rw_dout___rdy___width 1
#define reg_pio_rw_dout___rdy___bit 15
#define reg_pio_rw_dout_offset 80
/* Register rw_oe, scope pio, type rw */
#define reg_pio_rw_oe___data___lsb 0
#define reg_pio_rw_oe___data___width 8
#define reg_pio_rw_oe___rd_n___lsb 8
#define reg_pio_rw_oe___rd_n___width 1
#define reg_pio_rw_oe___rd_n___bit 8
#define reg_pio_rw_oe___wr_n___lsb 9
#define reg_pio_rw_oe___wr_n___width 1
#define reg_pio_rw_oe___wr_n___bit 9
#define reg_pio_rw_oe___a0___lsb 10
#define reg_pio_rw_oe___a0___width 1
#define reg_pio_rw_oe___a0___bit 10
#define reg_pio_rw_oe___a1___lsb 11
#define reg_pio_rw_oe___a1___width 1
#define reg_pio_rw_oe___a1___bit 11
#define reg_pio_rw_oe___ce0_n___lsb 12
#define reg_pio_rw_oe___ce0_n___width 1
#define reg_pio_rw_oe___ce0_n___bit 12
#define reg_pio_rw_oe___ce1_n___lsb 13
#define reg_pio_rw_oe___ce1_n___width 1
#define reg_pio_rw_oe___ce1_n___bit 13
#define reg_pio_rw_oe___ce2_n___lsb 14
#define reg_pio_rw_oe___ce2_n___width 1
#define reg_pio_rw_oe___ce2_n___bit 14
#define reg_pio_rw_oe___rdy___lsb 15
#define reg_pio_rw_oe___rdy___width 1
#define reg_pio_rw_oe___rdy___bit 15
#define reg_pio_rw_oe_offset 84
/* Register rw_man_ctrl, scope pio, type rw */
#define reg_pio_rw_man_ctrl___data___lsb 0
#define reg_pio_rw_man_ctrl___data___width 8
#define reg_pio_rw_man_ctrl___rd_n___lsb 8
#define reg_pio_rw_man_ctrl___rd_n___width 1
#define reg_pio_rw_man_ctrl___rd_n___bit 8
#define reg_pio_rw_man_ctrl___wr_n___lsb 9
#define reg_pio_rw_man_ctrl___wr_n___width 1
#define reg_pio_rw_man_ctrl___wr_n___bit 9
#define reg_pio_rw_man_ctrl___a0___lsb 10
#define reg_pio_rw_man_ctrl___a0___width 1
#define reg_pio_rw_man_ctrl___a0___bit 10
#define reg_pio_rw_man_ctrl___a1___lsb 11
#define reg_pio_rw_man_ctrl___a1___width 1
#define reg_pio_rw_man_ctrl___a1___bit 11
#define reg_pio_rw_man_ctrl___ce0_n___lsb 12
#define reg_pio_rw_man_ctrl___ce0_n___width 1
#define reg_pio_rw_man_ctrl___ce0_n___bit 12
#define reg_pio_rw_man_ctrl___ce1_n___lsb 13
#define reg_pio_rw_man_ctrl___ce1_n___width 1
#define reg_pio_rw_man_ctrl___ce1_n___bit 13
#define reg_pio_rw_man_ctrl___ce2_n___lsb 14
#define reg_pio_rw_man_ctrl___ce2_n___width 1
#define reg_pio_rw_man_ctrl___ce2_n___bit 14
#define reg_pio_rw_man_ctrl___rdy___lsb 15
#define reg_pio_rw_man_ctrl___rdy___width 1
#define reg_pio_rw_man_ctrl___rdy___bit 15
#define reg_pio_rw_man_ctrl_offset 88
/* Register r_din, scope pio, type r */
#define reg_pio_r_din___data___lsb 0
#define reg_pio_r_din___data___width 8
#define reg_pio_r_din___rd_n___lsb 8
#define reg_pio_r_din___rd_n___width 1
#define reg_pio_r_din___rd_n___bit 8
#define reg_pio_r_din___wr_n___lsb 9
#define reg_pio_r_din___wr_n___width 1
#define reg_pio_r_din___wr_n___bit 9
#define reg_pio_r_din___a0___lsb 10
#define reg_pio_r_din___a0___width 1
#define reg_pio_r_din___a0___bit 10
#define reg_pio_r_din___a1___lsb 11
#define reg_pio_r_din___a1___width 1
#define reg_pio_r_din___a1___bit 11
#define reg_pio_r_din___ce0_n___lsb 12
#define reg_pio_r_din___ce0_n___width 1
#define reg_pio_r_din___ce0_n___bit 12
#define reg_pio_r_din___ce1_n___lsb 13
#define reg_pio_r_din___ce1_n___width 1
#define reg_pio_r_din___ce1_n___bit 13
#define reg_pio_r_din___ce2_n___lsb 14
#define reg_pio_r_din___ce2_n___width 1
#define reg_pio_r_din___ce2_n___bit 14
#define reg_pio_r_din___rdy___lsb 15
#define reg_pio_r_din___rdy___width 1
#define reg_pio_r_din___rdy___bit 15
#define reg_pio_r_din_offset 92
/* Register r_stat, scope pio, type r */
#define reg_pio_r_stat___busy___lsb 0
#define reg_pio_r_stat___busy___width 1
#define reg_pio_r_stat___busy___bit 0
#define reg_pio_r_stat_offset 96
/* Register rw_intr_mask, scope pio, type rw */
#define reg_pio_rw_intr_mask___rdy___lsb 0
#define reg_pio_rw_intr_mask___rdy___width 1
#define reg_pio_rw_intr_mask___rdy___bit 0
#define reg_pio_rw_intr_mask_offset 100
/* Register rw_ack_intr, scope pio, type rw */
#define reg_pio_rw_ack_intr___rdy___lsb 0
#define reg_pio_rw_ack_intr___rdy___width 1
#define reg_pio_rw_ack_intr___rdy___bit 0
#define reg_pio_rw_ack_intr_offset 104
/* Register r_intr, scope pio, type r */
#define reg_pio_r_intr___rdy___lsb 0
#define reg_pio_r_intr___rdy___width 1
#define reg_pio_r_intr___rdy___bit 0
#define reg_pio_r_intr_offset 108
/* Register r_masked_intr, scope pio, type r */
#define reg_pio_r_masked_intr___rdy___lsb 0
#define reg_pio_r_masked_intr___rdy___width 1
#define reg_pio_r_masked_intr___rdy___bit 0
#define reg_pio_r_masked_intr_offset 112
/* Constants */
#define regk_pio_a2 0x00000003
#define regk_pio_no 0x00000000
#define regk_pio_normal 0x00000000
#define regk_pio_rd 0x00000001
#define regk_pio_rw_ce0_cfg_default 0x00000000
#define regk_pio_rw_ce1_cfg_default 0x00000000
#define regk_pio_rw_ce2_cfg_default 0x00000000
#define regk_pio_rw_intr_mask_default 0x00000000
#define regk_pio_rw_man_ctrl_default 0x00000000
#define regk_pio_rw_oe_default 0x00000000
#define regk_pio_wr 0x00000002
#define regk_pio_wr_ce2 0x00000003
#define regk_pio_yes 0x00000001
#define regk_pio_yes_all 0x000000ff
#endif /* __pio_defs_asm_h */
include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __reg_map_asm_h
#define __reg_map_asm_h
/*
* This file is autogenerated from
* file: reg.rmap
*
* by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#define regi_ccd 0xb0000000
#define regi_ccd_top 0xb0000000
#define regi_ccd_dp 0xb0000400
#define regi_ccd_stat 0xb0000800
#define regi_ccd_tg 0xb0001000
#define regi_cfg 0xb0002000
#define regi_clkgen 0xb0004000
#define regi_ddr2_ctrl 0xb0006000
#define regi_dma0 0xb0008000
#define regi_dma1 0xb000a000
#define regi_dma11 0xb000c000
#define regi_dma2 0xb000e000
#define regi_dma3 0xb0010000
#define regi_dma4 0xb0012000
#define regi_dma5 0xb0014000
#define regi_dma6 0xb0016000
#define regi_dma7 0xb0018000
#define regi_dma9 0xb001a000
#define regi_eth 0xb001c000
#define regi_gio 0xb0020000
#define regi_h264 0xb0022000
#define regi_hist 0xb0026000
#define regi_iop 0xb0028000
#define regi_iop_version 0xb0028000
#define regi_iop_fifo_in_extra 0xb0028040
#define regi_iop_fifo_out_extra 0xb0028080
#define regi_iop_trigger_grp0 0xb00280c0
#define regi_iop_trigger_grp1 0xb0028100
#define regi_iop_trigger_grp2 0xb0028140
#define regi_iop_trigger_grp3 0xb0028180
#define regi_iop_trigger_grp4 0xb00281c0
#define regi_iop_trigger_grp5 0xb0028200
#define regi_iop_trigger_grp6 0xb0028240
#define regi_iop_trigger_grp7 0xb0028280
#define regi_iop_crc_par 0xb0028300
#define regi_iop_dmc_in 0xb0028380
#define regi_iop_dmc_out 0xb0028400
#define regi_iop_fifo_in 0xb0028480
#define regi_iop_fifo_out 0xb0028500
#define regi_iop_scrc_in 0xb0028580
#define regi_iop_scrc_out 0xb0028600
#define regi_iop_timer_grp0 0xb0028680
#define regi_iop_timer_grp1 0xb0028700
#define regi_iop_sap_in 0xb0028800
#define regi_iop_sap_out 0xb0028900
#define regi_iop_spu 0xb0028a00
#define regi_iop_sw_cfg 0xb0028b00
#define regi_iop_sw_cpu 0xb0028c00
#define regi_iop_sw_mpu 0xb0028d00
#define regi_iop_sw_spu 0xb0028e00
#define regi_iop_mpu 0xb0029000
#define regi_irq 0xb002a000
#define regi_jpeg 0xb002c000
#define regi_l2cache 0xb0030000
#define regi_marb_bar 0xb0032000
#define regi_marb_bar_bp0 0xb0032140
#define regi_marb_bar_bp1 0xb0032180
#define regi_marb_bar_bp2 0xb00321c0
#define regi_marb_bar_bp3 0xb0032200
#define regi_marb_foo 0xb0034000
#define regi_marb_foo_bp0 0xb0034280
#define regi_marb_foo_bp1 0xb00342c0
#define regi_marb_foo_bp2 0xb0034300
#define regi_marb_foo_bp3 0xb0034340
#define regi_pinmux 0xb0038000
#define regi_pio 0xb0036000
#define regi_sclr 0xb003a000
#define regi_sclr_fifo 0xb003c000
#define regi_ser0 0xb003e000
#define regi_ser1 0xb0040000
#define regi_ser2 0xb0042000
#define regi_ser3 0xb0044000
#define regi_ser4 0xb0046000
#define regi_sser 0xb0048000
#define regi_strcop 0xb004a000
#define regi_strdma0 0xb004e000
#define regi_strdma1 0xb0050000
#define regi_strdma2 0xb0052000
#define regi_strdma3 0xb0054000
#define regi_strdma5 0xb0056000
#define regi_strmux 0xb004c000
#define regi_timer0 0xb0058000
#define regi_timer1 0xb005a000
#define regi_trace 0xb005c000
#define regi_vin 0xb005e000
#define regi_vout 0xb0060000
#endif /* __reg_map_asm_h */
include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __timer_defs_asm_h
#define __timer_defs_asm_h
/*
* This file is autogenerated from
* file: timer.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_tmr0_div, scope timer, type rw */
#define reg_timer_rw_tmr0_div_offset 0
/* Register r_tmr0_data, scope timer, type r */
#define reg_timer_r_tmr0_data_offset 4
/* Register rw_tmr0_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr0_ctrl___op___lsb 0
#define reg_timer_rw_tmr0_ctrl___op___width 2
#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
#define reg_timer_rw_tmr0_ctrl___freq___width 3
#define reg_timer_rw_tmr0_ctrl_offset 8
/* Register rw_tmr1_div, scope timer, type rw */
#define reg_timer_rw_tmr1_div_offset 16
/* Register r_tmr1_data, scope timer, type r */
#define reg_timer_r_tmr1_data_offset 20
/* Register rw_tmr1_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr1_ctrl___op___lsb 0
#define reg_timer_rw_tmr1_ctrl___op___width 2
#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
#define reg_timer_rw_tmr1_ctrl___freq___width 3
#define reg_timer_rw_tmr1_ctrl_offset 24
/* Register rs_cnt_data, scope timer, type rs */
#define reg_timer_rs_cnt_data___tmr___lsb 0
#define reg_timer_rs_cnt_data___tmr___width 24
#define reg_timer_rs_cnt_data___cnt___lsb 24
#define reg_timer_rs_cnt_data___cnt___width 8
#define reg_timer_rs_cnt_data_offset 32
/* Register r_cnt_data, scope timer, type r */
#define reg_timer_r_cnt_data___tmr___lsb 0
#define reg_timer_r_cnt_data___tmr___width 24
#define reg_timer_r_cnt_data___cnt___lsb 24
#define reg_timer_r_cnt_data___cnt___width 8
#define reg_timer_r_cnt_data_offset 36
/* Register rw_cnt_cfg, scope timer, type rw */
#define reg_timer_rw_cnt_cfg___clk___lsb 0
#define reg_timer_rw_cnt_cfg___clk___width 2
#define reg_timer_rw_cnt_cfg_offset 40
/* Register rw_trig, scope timer, type rw */
#define reg_timer_rw_trig_offset 48
/* Register rw_trig_cfg, scope timer, type rw */
#define reg_timer_rw_trig_cfg___tmr___lsb 0
#define reg_timer_rw_trig_cfg___tmr___width 2
#define reg_timer_rw_trig_cfg_offset 52
/* Register r_time, scope timer, type r */
#define reg_timer_r_time_offset 56
/* Register rw_out, scope timer, type rw */
#define reg_timer_rw_out___tmr___lsb 0
#define reg_timer_rw_out___tmr___width 2
#define reg_timer_rw_out_offset 60
/* Register rw_wd_ctrl, scope timer, type rw */
#define reg_timer_rw_wd_ctrl___cnt___lsb 0
#define reg_timer_rw_wd_ctrl___cnt___width 8
#define reg_timer_rw_wd_ctrl___cmd___lsb 8
#define reg_timer_rw_wd_ctrl___cmd___width 1
#define reg_timer_rw_wd_ctrl___cmd___bit 8
#define reg_timer_rw_wd_ctrl___key___lsb 9
#define reg_timer_rw_wd_ctrl___key___width 7
#define reg_timer_rw_wd_ctrl_offset 64
/* Register r_wd_stat, scope timer, type r */
#define reg_timer_r_wd_stat___cnt___lsb 0
#define reg_timer_r_wd_stat___cnt___width 8
#define reg_timer_r_wd_stat___cmd___lsb 8
#define reg_timer_r_wd_stat___cmd___width 1
#define reg_timer_r_wd_stat___cmd___bit 8
#define reg_timer_r_wd_stat_offset 68
/* Register rw_intr_mask, scope timer, type rw */
#define reg_timer_rw_intr_mask___tmr0___lsb 0
#define reg_timer_rw_intr_mask___tmr0___width 1
#define reg_timer_rw_intr_mask___tmr0___bit 0
#define reg_timer_rw_intr_mask___tmr1___lsb 1
#define reg_timer_rw_intr_mask___tmr1___width 1
#define reg_timer_rw_intr_mask___tmr1___bit 1
#define reg_timer_rw_intr_mask___cnt___lsb 2
#define reg_timer_rw_intr_mask___cnt___width 1
#define reg_timer_rw_intr_mask___cnt___bit 2
#define reg_timer_rw_intr_mask___trig___lsb 3
#define reg_timer_rw_intr_mask___trig___width 1
#define reg_timer_rw_intr_mask___trig___bit 3
#define reg_timer_rw_intr_mask_offset 72
/* Register rw_ack_intr, scope timer, type rw */
#define reg_timer_rw_ack_intr___tmr0___lsb 0
#define reg_timer_rw_ack_intr___tmr0___width 1
#define reg_timer_rw_ack_intr___tmr0___bit 0
#define reg_timer_rw_ack_intr___tmr1___lsb 1
#define reg_timer_rw_ack_intr___tmr1___width 1
#define reg_timer_rw_ack_intr___tmr1___bit 1
#define reg_timer_rw_ack_intr___cnt___lsb 2
#define reg_timer_rw_ack_intr___cnt___width 1
#define reg_timer_rw_ack_intr___cnt___bit 2
#define reg_timer_rw_ack_intr___trig___lsb 3
#define reg_timer_rw_ack_intr___trig___width 1
#define reg_timer_rw_ack_intr___trig___bit 3
#define reg_timer_rw_ack_intr_offset 76
/* Register r_intr, scope timer, type r */
#define reg_timer_r_intr___tmr0___lsb 0
#define reg_timer_r_intr___tmr0___width 1
#define reg_timer_r_intr___tmr0___bit 0
#define reg_timer_r_intr___tmr1___lsb 1
#define reg_timer_r_intr___tmr1___width 1
#define reg_timer_r_intr___tmr1___bit 1
#define reg_timer_r_intr___cnt___lsb 2
#define reg_timer_r_intr___cnt___width 1
#define reg_timer_r_intr___cnt___bit 2
#define reg_timer_r_intr___trig___lsb 3
#define reg_timer_r_intr___trig___width 1
#define reg_timer_r_intr___trig___bit 3
#define reg_timer_r_intr_offset 80
/* Register r_masked_intr, scope timer, type r */
#define reg_timer_r_masked_intr___tmr0___lsb 0
#define reg_timer_r_masked_intr___tmr0___width 1
#define reg_timer_r_masked_intr___tmr0___bit 0
#define reg_timer_r_masked_intr___tmr1___lsb 1
#define reg_timer_r_masked_intr___tmr1___width 1
#define reg_timer_r_masked_intr___tmr1___bit 1
#define reg_timer_r_masked_intr___cnt___lsb 2
#define reg_timer_r_masked_intr___cnt___width 1
#define reg_timer_r_masked_intr___cnt___bit 2
#define reg_timer_r_masked_intr___trig___lsb 3
#define reg_timer_r_masked_intr___trig___width 1
#define reg_timer_r_masked_intr___trig___bit 3
#define reg_timer_r_masked_intr_offset 84
/* Register rw_test, scope timer, type rw */
#define reg_timer_rw_test___dis___lsb 0
#define reg_timer_rw_test___dis___width 1
#define reg_timer_rw_test___dis___bit 0
#define reg_timer_rw_test___en___lsb 1
#define reg_timer_rw_test___en___width 1
#define reg_timer_rw_test___en___bit 1
#define reg_timer_rw_test_offset 88
/* Constants */
#define regk_timer_ext 0x00000001
#define regk_timer_f100 0x00000007
#define regk_timer_f29_493 0x00000004
#define regk_timer_f32 0x00000005
#define regk_timer_f32_768 0x00000006
#define regk_timer_f90 0x00000003
#define regk_timer_hold 0x00000001
#define regk_timer_ld 0x00000000
#define regk_timer_no 0x00000000
#define regk_timer_off 0x00000000
#define regk_timer_run 0x00000002
#define regk_timer_rw_cnt_cfg_default 0x00000000
#define regk_timer_rw_intr_mask_default 0x00000000
#define regk_timer_rw_out_default 0x00000000
#define regk_timer_rw_test_default 0x00000000
#define regk_timer_rw_tmr0_ctrl_default 0x00000000
#define regk_timer_rw_tmr1_ctrl_default 0x00000000
#define regk_timer_rw_trig_cfg_default 0x00000000
#define regk_timer_start 0x00000001
#define regk_timer_stop 0x00000000
#define regk_timer_time 0x00000001
#define regk_timer_tmr0 0x00000002
#define regk_timer_tmr1 0x00000003
#define regk_timer_vclk 0x00000002
#define regk_timer_yes 0x00000001
#endif /* __timer_defs_asm_h */
include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __clkgen_defs_h
#define __clkgen_defs_h
/*
* This file is autogenerated from
* file: clkgen.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope clkgen */
/* Register r_bootsel, scope clkgen, type r */
typedef struct {
unsigned int boot_mode : 5;
unsigned int intern_main_clk : 1;
unsigned int extern_usb2_clk : 1;
unsigned int dummy1 : 25;
} reg_clkgen_r_bootsel;
#define REG_RD_ADDR_clkgen_r_bootsel 0
/* Register rw_clk_ctrl, scope clkgen, type rw */
typedef struct {
unsigned int pll : 1;
unsigned int cpu : 1;
unsigned int iop_usb : 1;
unsigned int vin : 1;
unsigned int sclr : 1;
unsigned int h264 : 1;
unsigned int ddr2 : 1;
unsigned int vout_hist : 1;
unsigned int eth : 1;
unsigned int ccd_tg_200 : 1;
unsigned int dma0_1_eth : 1;
unsigned int ccd_tg_100 : 1;
unsigned int jpeg : 1;
unsigned int sser_ser_dma6_7 : 1;
unsigned int strdma0_2_video : 1;
unsigned int dma2_3_strcop : 1;
unsigned int dma4_5_iop : 1;
unsigned int dma9_11 : 1;
unsigned int memarb_bar_ddr : 1;
unsigned int sclr_h264 : 1;
unsigned int dummy1 : 12;
} reg_clkgen_rw_clk_ctrl;
#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
/* Constants */
enum {
regk_clkgen_eth1000_rx = 0x0000000c,
regk_clkgen_eth1000_tx = 0x0000000e,
regk_clkgen_eth100_rx = 0x0000001d,
regk_clkgen_eth100_rx_half = 0x0000001c,
regk_clkgen_eth100_tx = 0x0000001f,
regk_clkgen_eth100_tx_half = 0x0000001e,
regk_clkgen_nand_3_2 = 0x00000000,
regk_clkgen_nand_3_2_0x30 = 0x00000002,
regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
regk_clkgen_nand_3_2_pll = 0x00000010,
regk_clkgen_nand_3_3 = 0x00000001,
regk_clkgen_nand_3_3_0x30 = 0x00000003,
regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
regk_clkgen_nand_3_3_pll = 0x00000011,
regk_clkgen_nand_4_2 = 0x00000004,
regk_clkgen_nand_4_2_0x30 = 0x00000006,
regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
regk_clkgen_nand_4_2_pll = 0x00000014,
regk_clkgen_nand_4_3 = 0x00000005,
regk_clkgen_nand_4_3_0x30 = 0x00000007,
regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
regk_clkgen_nand_4_3_pll = 0x00000015,
regk_clkgen_nand_5_2 = 0x00000008,
regk_clkgen_nand_5_2_0x30 = 0x0000000a,
regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
regk_clkgen_nand_5_2_pll = 0x00000018,
regk_clkgen_nand_5_3 = 0x00000009,
regk_clkgen_nand_5_3_0x30 = 0x0000000b,
regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
regk_clkgen_nand_5_3_pll = 0x00000019,
regk_clkgen_no = 0x00000000,
regk_clkgen_rw_clk_ctrl_default = 0x00000002,
regk_clkgen_ser = 0x0000000d,
regk_clkgen_ser_pll = 0x0000000f,
regk_clkgen_yes = 0x00000001
};
#endif /* __clkgen_defs_h */
include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __ddr2_defs_h
#define __ddr2_defs_h
/*
* This file is autogenerated from
* file: ddr2.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope ddr2 */
/* Register rw_cfg, scope ddr2, type rw */
typedef struct {
unsigned int col_width : 4;
unsigned int nr_banks : 1;
unsigned int bw : 1;
unsigned int nr_ref : 4;
unsigned int ref_interval : 11;
unsigned int odt_ctrl : 2;
unsigned int odt_mem : 1;
unsigned int imp_strength : 1;
unsigned int auto_imp_cal : 1;
unsigned int imp_cal_override : 1;
unsigned int dll_override : 1;
unsigned int dummy1 : 4;
} reg_ddr2_rw_cfg;
#define REG_RD_ADDR_ddr2_rw_cfg 0
#define REG_WR_ADDR_ddr2_rw_cfg 0
/* Register rw_timing, scope ddr2, type rw */
typedef struct {
unsigned int wr : 3;
unsigned int rcd : 3;
unsigned int rp : 3;
unsigned int ras : 4;
unsigned int rfc : 7;
unsigned int rc : 5;
unsigned int rtp : 2;
unsigned int rtw : 3;
unsigned int wtr : 2;
} reg_ddr2_rw_timing;
#define REG_RD_ADDR_ddr2_rw_timing 4
#define REG_WR_ADDR_ddr2_rw_timing 4
/* Register rw_latency, scope ddr2, type rw */
typedef struct {
unsigned int cas : 3;
unsigned int additive : 3;
unsigned int dummy1 : 26;
} reg_ddr2_rw_latency;
#define REG_RD_ADDR_ddr2_rw_latency 8
#define REG_WR_ADDR_ddr2_rw_latency 8
/* Register rw_phy_cfg, scope ddr2, type rw */
typedef struct {
unsigned int en : 1;
unsigned int dummy1 : 31;
} reg_ddr2_rw_phy_cfg;
#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
/* Register rw_phy_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int rst : 1;
unsigned int cal_rst : 1;
unsigned int cal_start : 1;
unsigned int dummy1 : 29;
} reg_ddr2_rw_phy_ctrl;
#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
/* Register rw_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int mrs_data : 16;
unsigned int cmd : 8;
unsigned int dummy1 : 8;
} reg_ddr2_rw_ctrl;
#define REG_RD_ADDR_ddr2_rw_ctrl 20
#define REG_WR_ADDR_ddr2_rw_ctrl 20
/* Register rw_pwr_down, scope ddr2, type rw */
typedef struct {
unsigned int self_ref : 2;
unsigned int phy_en : 1;
unsigned int dummy1 : 29;
} reg_ddr2_rw_pwr_down;
#define REG_RD_ADDR_ddr2_rw_pwr_down 24
#define REG_WR_ADDR_ddr2_rw_pwr_down 24
/* Register r_stat, scope ddr2, type r */
typedef struct {
unsigned int dll_lock : 1;
unsigned int dll_delay_code : 7;
unsigned int imp_cal_done : 1;
unsigned int imp_cal_fault : 1;
unsigned int cal_imp_pu : 4;
unsigned int cal_imp_pd : 4;
unsigned int dummy1 : 14;
} reg_ddr2_r_stat;
#define REG_RD_ADDR_ddr2_r_stat 28
/* Register rw_imp_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int imp_pu : 4;
unsigned int imp_pd : 4;
unsigned int dummy1 : 24;
} reg_ddr2_rw_imp_ctrl;
#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
#define STRIDE_ddr2_rw_dll_ctrl 4
/* Register rw_dll_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int mode : 1;
unsigned int clk_delay : 7;
unsigned int dummy1 : 24;
} reg_ddr2_rw_dll_ctrl;
#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int dqs90_delay : 7;
unsigned int dqs180_delay : 7;
unsigned int dqs270_delay : 7;
unsigned int dqs360_delay : 7;
unsigned int dummy1 : 4;
} reg_ddr2_rw_dqs_dll_ctrl;
#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
/* Constants */
enum {
regk_ddr2_al0 = 0x00000000,
regk_ddr2_al1 = 0x00000008,
regk_ddr2_al2 = 0x00000010,
regk_ddr2_al3 = 0x00000018,
regk_ddr2_al4 = 0x00000020,
regk_ddr2_auto = 0x00000003,
regk_ddr2_bank4 = 0x00000000,
regk_ddr2_bank8 = 0x00000001,
regk_ddr2_bl4 = 0x00000002,
regk_ddr2_bl8 = 0x00000003,
regk_ddr2_bt_il = 0x00000008,
regk_ddr2_bt_seq = 0x00000000,
regk_ddr2_bw16 = 0x00000001,
regk_ddr2_bw32 = 0x00000000,
regk_ddr2_cas2 = 0x00000020,
regk_ddr2_cas3 = 0x00000030,
regk_ddr2_cas4 = 0x00000040,
regk_ddr2_cas5 = 0x00000050,
regk_ddr2_deselect = 0x000000c0,
regk_ddr2_dic_weak = 0x00000002,
regk_ddr2_direct = 0x00000001,
regk_ddr2_dis = 0x00000000,
regk_ddr2_dll_dis = 0x00000001,
regk_ddr2_dll_en = 0x00000000,
regk_ddr2_dll_rst = 0x00000100,
regk_ddr2_emrs = 0x00000081,
regk_ddr2_emrs2 = 0x00000082,
regk_ddr2_emrs3 = 0x00000083,
regk_ddr2_full = 0x00000001,
regk_ddr2_hi_ref_rate = 0x00000080,
regk_ddr2_mrs = 0x00000080,
regk_ddr2_no = 0x00000000,
regk_ddr2_nop = 0x000000b8,
regk_ddr2_ocd_adj = 0x00000200,
regk_ddr2_ocd_default = 0x00000380,
regk_ddr2_ocd_drive0 = 0x00000100,
regk_ddr2_ocd_drive1 = 0x00000080,
regk_ddr2_ocd_exit = 0x00000000,
regk_ddr2_odt_dis = 0x00000000,
regk_ddr2_offs = 0x00000000,
regk_ddr2_pre = 0x00000090,
regk_ddr2_pre_all = 0x00000400,
regk_ddr2_pwr_down_fast = 0x00000000,
regk_ddr2_pwr_down_slow = 0x00001000,
regk_ddr2_ref = 0x00000088,
regk_ddr2_rtt150 = 0x00000040,
regk_ddr2_rtt50 = 0x00000044,
regk_ddr2_rtt75 = 0x00000004,
regk_ddr2_rw_cfg_default = 0x00186000,
regk_ddr2_rw_dll_ctrl_default = 0x00000000,
regk_ddr2_rw_dll_ctrl_size = 0x00000004,
regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
regk_ddr2_rw_latency_default = 0x00000000,
regk_ddr2_rw_phy_cfg_default = 0x00000000,
regk_ddr2_rw_pwr_down_default = 0x00000000,
regk_ddr2_rw_timing_default = 0x00000000,
regk_ddr2_s1Gb = 0x0000001a,
regk_ddr2_s256Mb = 0x0000000f,
regk_ddr2_s2Gb = 0x00000027,
regk_ddr2_s4Gb = 0x00000042,
regk_ddr2_s512Mb = 0x00000015,
regk_ddr2_temp0_85 = 0x00000618,
regk_ddr2_temp85_95 = 0x0000030c,
regk_ddr2_term150 = 0x00000002,
regk_ddr2_term50 = 0x00000003,
regk_ddr2_term75 = 0x00000001,
regk_ddr2_test = 0x00000080,
regk_ddr2_weak = 0x00000000,
regk_ddr2_wr2 = 0x00000200,
regk_ddr2_wr3 = 0x00000400,
regk_ddr2_yes = 0x00000001
};
#endif /* __ddr2_defs_h */
include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h 0 → 100644
浏览文件 @ 58d08319
此差异已折叠。
include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h 0 → 100644
浏览文件 @ 58d08319
/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr
from intr_vect.r */
#ifndef _INTR_VECT_R
#define _INTR_VECT_R
#define TIMER0_INTR_VECT 0x31
#define TIMER1_INTR_VECT 0x32
#define DMA0_INTR_VECT 0x33
#define DMA1_INTR_VECT 0x34
#define DMA2_INTR_VECT 0x35
#define DMA3_INTR_VECT 0x36
#define DMA4_INTR_VECT 0x37
#define DMA5_INTR_VECT 0x38
#define DMA6_INTR_VECT 0x39
#define DMA7_INTR_VECT 0x3a
#define DMA9_INTR_VECT 0x3b
#define DMA11_INTR_VECT 0x3c
#define GIO_INTR_VECT 0x3d
#define IOP0_INTR_VECT 0x3e
#define IOP1_INTR_VECT 0x3f
#define SER0_INTR_VECT 0x40
#define SER1_INTR_VECT 0x41
#define SER2_INTR_VECT 0x42
#define SER3_INTR_VECT 0x43
#define SER4_INTR_VECT 0x44
#define SSER_INTR_VECT 0x45
#define STRDMA0_INTR_VECT 0x46
#define STRDMA1_INTR_VECT 0x47
#define STRDMA2_INTR_VECT 0x48
#define STRDMA3_INTR_VECT 0x49
#define STRDMA5_INTR_VECT 0x4a
#define VIN_INTR_VECT 0x4b
#define VOUT_INTR_VECT 0x4c
#define JPEG_INTR_VECT 0x4d
#define H264_INTR_VECT 0x4e
#define HISTO_INTR_VECT 0x4f
#define CCD_INTR_VECT 0x50
#define ETH_INTR_VECT 0x51
#define MEMARB_BAR_INTR_VECT 0x52
#define MEMARB_FOO_INTR_VECT 0x53
#define PIO_INTR_VECT 0x54
#define SCLR_INTR_VECT 0x55
#define SCLR_FIFO_INTR_VECT 0x56
#define IPI_INTR_VECT 0x57
#define NBR_INTR_VECT 0x58
#endif
include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __intr_vect_defs_h
#define __intr_vect_defs_h
/*
* This file is autogenerated from
* file: intr_vect.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope intr_vect */
#define STRIDE_intr_vect_rw_mask 4
/* Register rw_mask0, scope intr_vect, type rw */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_rw_mask0;
#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
#define REG_RD_ADDR_intr_vect_rw_mask 0
#define REG_WR_ADDR_intr_vect_rw_mask 0
#define REG_RD_ADDR_intr_vect_rw_mask0 0
#define REG_WR_ADDR_intr_vect_rw_mask0 0
#define STRIDE_intr_vect_r_vect 4
/* Register r_vect0, scope intr_vect, type r */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_r_vect0;
#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
#define REG_RD_ADDR_intr_vect_r_vect 8
#define REG_RD_ADDR_intr_vect_r_vect0 8
#define STRIDE_intr_vect_r_masked_vect 4
/* Register r_masked_vect0, scope intr_vect, type r */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_r_masked_vect0;
#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
#define REG_RD_ADDR_intr_vect_r_masked_vect 16
#define STRIDE_intr_vect_rw_xmask 4
/* Register rw_xmask0, scope intr_vect, type rw */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_rw_xmask0;
#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
#define REG_RD_ADDR_intr_vect_rw_xmask0 24
#define REG_WR_ADDR_intr_vect_rw_xmask0 24
#define REG_RD_ADDR_intr_vect_rw_xmask 24
#define REG_WR_ADDR_intr_vect_rw_xmask 24
/* Register rw_mask1, scope intr_vect, type rw */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_rw_mask1;
#define REG_RD_ADDR_intr_vect_rw_mask1 4
#define REG_WR_ADDR_intr_vect_rw_mask1 4
/* Register r_vect1, scope intr_vect, type r */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_r_vect1;
#define REG_RD_ADDR_intr_vect_r_vect1 12
/* Register r_masked_vect1, scope intr_vect, type r */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_r_masked_vect1;
#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
/* Register rw_xmask1, scope intr_vect, type rw */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_rw_xmask1;
#define REG_RD_ADDR_intr_vect_rw_xmask1 28
#define REG_WR_ADDR_intr_vect_rw_xmask1 28
/* Register rw_xmask_ctrl, scope intr_vect, type rw */
typedef struct {
unsigned int en : 1;
unsigned int dummy1 : 31;
} reg_intr_vect_rw_xmask_ctrl;
#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
/* Register r_nmi, scope intr_vect, type r */
typedef struct {
unsigned int watchdog0 : 1;
unsigned int watchdog1 : 1;
unsigned int dummy1 : 30;
} reg_intr_vect_r_nmi;
#define REG_RD_ADDR_intr_vect_r_nmi 64
/* Register r_guru, scope intr_vect, type r */
typedef struct {
unsigned int jtag : 1;
unsigned int dummy1 : 31;
} reg_intr_vect_r_guru;
#define REG_RD_ADDR_intr_vect_r_guru 68
/* Register rw_ipi, scope intr_vect, type rw */
typedef struct
{
unsigned int vector;
} reg_intr_vect_rw_ipi;
#define REG_RD_ADDR_intr_vect_rw_ipi 72
#define REG_WR_ADDR_intr_vect_rw_ipi 72
/* Constants */
enum {
regk_intr_vect_no = 0x00000000,
regk_intr_vect_rw_mask0_default = 0x00000000,
regk_intr_vect_rw_mask1_default = 0x00000000,
regk_intr_vect_rw_xmask0_default = 0x00000000,
regk_intr_vect_rw_xmask1_default = 0x00000000,
regk_intr_vect_rw_xmask_ctrl_default = 0x00000000,
regk_intr_vect_yes = 0x00000001
};
#endif /* __intr_vect_defs_h */
include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h 0 → 100644
浏览文件 @ 58d08319
/* Autogenerated Changes here will be lost!
* generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
*/
#define iop_version 0
#define iop_fifo_in_extra 64
#define iop_fifo_out_extra 128
#define iop_trigger_grp0 192
#define iop_trigger_grp1 256
#define iop_trigger_grp2 320
#define iop_trigger_grp3 384
#define iop_trigger_grp4 448
#define iop_trigger_grp5 512
#define iop_trigger_grp6 576
#define iop_trigger_grp7 640
#define iop_crc_par 768
#define iop_dmc_in 896
#define iop_dmc_out 1024
#define iop_fifo_in 1152
#define iop_fifo_out 1280
#define iop_scrc_in 1408
#define iop_scrc_out 1536
#define iop_timer_grp0 1664
#define iop_timer_grp1 1792
#define iop_sap_in 2048
#define iop_sap_out 2304
#define iop_spu 2560
#define iop_sw_cfg 2816
#define iop_sw_cpu 3072
#define iop_sw_mpu 3328
#define iop_sw_spu 3584
#define iop_mpu 4096
include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __iop_sap_in_defs_asm_h
#define __iop_sap_in_defs_asm_h
/*
* This file is autogenerated from
* file: iop_sap_in.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
#define STRIDE_iop_sap_in_rw_bus_byte 4
/* Register rw_bus_byte, scope iop_sap_in, type rw */
#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
#define reg_iop_sap_in_rw_bus_byte___delay___width 2
#define reg_iop_sap_in_rw_bus_byte_offset 0
#define STRIDE_iop_sap_in_rw_gio 4
/* Register rw_gio, scope iop_sap_in, type rw */
#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
#define reg_iop_sap_in_rw_gio___sync_sel___width 2
#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
#define reg_iop_sap_in_rw_gio___sync_edge___width 2
#define reg_iop_sap_in_rw_gio___delay___lsb 7
#define reg_iop_sap_in_rw_gio___delay___width 2
#define reg_iop_sap_in_rw_gio___logic___lsb 9
#define reg_iop_sap_in_rw_gio___logic___width 2
#define reg_iop_sap_in_rw_gio_offset 16
/* Constants */
#define regk_iop_sap_in_and 0x00000002
#define regk_iop_sap_in_ext_clk200 0x00000003
#define regk_iop_sap_in_gio0 0x00000000
#define regk_iop_sap_in_gio12 0x00000003
#define regk_iop_sap_in_gio16 0x00000004
#define regk_iop_sap_in_gio20 0x00000005
#define regk_iop_sap_in_gio24 0x00000006
#define regk_iop_sap_in_gio28 0x00000007
#define regk_iop_sap_in_gio4 0x00000001
#define regk_iop_sap_in_gio8 0x00000002
#define regk_iop_sap_in_inv 0x00000001
#define regk_iop_sap_in_neg 0x00000002
#define regk_iop_sap_in_no 0x00000000
#define regk_iop_sap_in_no_del_ext_clk200 0x00000002
#define regk_iop_sap_in_none 0x00000000
#define regk_iop_sap_in_one 0x00000001
#define regk_iop_sap_in_or 0x00000003
#define regk_iop_sap_in_pos 0x00000001
#define regk_iop_sap_in_pos_neg 0x00000003
#define regk_iop_sap_in_rw_bus_byte_default 0x00000000
#define regk_iop_sap_in_rw_bus_byte_size 0x00000004
#define regk_iop_sap_in_rw_gio_default 0x00000000
#define regk_iop_sap_in_rw_gio_size 0x00000020
#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000
#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001
#define regk_iop_sap_in_tmr_clk200 0x00000001
#define regk_iop_sap_in_two 0x00000002
#define regk_iop_sap_in_two_clk200 0x00000000
#endif /* __iop_sap_in_defs_asm_h */
include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h 0 → 100644
浏览文件 @ 58d08319
#ifndef __iop_sap_out_defs_asm_h
#define __iop_sap_out_defs_asm_h
/*
* This file is autogenerated from
* file: iop_sap_out.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_gen_gated, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated_offset 0
/* Register rw_bus, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2
#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4
#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4
#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6
#define reg_iop_sap_out_rw_bus___byte0_delay___width 1
#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6
#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7
#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9
#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11
#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11
#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12
#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12
#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13
#define reg_iop_sap_out_rw_bus___byte1_delay___width 1
#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13
#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14
#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16
#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18
#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18
#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19
#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19
#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20
#define reg_iop_sap_out_rw_bus___byte2_delay___width 1
#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20
#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21
#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23
#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25
#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25
#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26
#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26
#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27
#define reg_iop_sap_out_rw_bus___byte3_delay___width 1
#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27
#define reg_iop_sap_out_rw_bus_offset 4
/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2
#define reg_iop_sap_out_rw_bus_lo_oe_offset 8
/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2
#define reg_iop_sap_out_rw_bus_hi_oe_offset 12
#define STRIDE_iop_sap_out_rw_gio 4
/* Register rw_gio, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2
#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5
#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1
#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5
#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6
#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6
#define reg_iop_sap_out_rw_gio___out_delay___lsb 7
#define reg_iop_sap_out_rw_gio___out_delay___width 1
#define reg_iop_sap_out_rw_gio___out_delay___bit 7
#define reg_iop_sap_out_rw_gio___out_logic___lsb 8
#define reg_iop_sap_out_rw_gio___out_logic___width 2
#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10
#define reg_iop_sap_out_rw_gio___out_logic_src___width 2
#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12
#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15
#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2
#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1
#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17
#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18
#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18
#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19
#define reg_iop_sap_out_rw_gio___oe_delay___width 1
#define reg_iop_sap_out_rw_gio___oe_delay___bit 19
#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
#define reg_iop_sap_out_rw_gio___oe_logic___width 2
#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22
#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2
#define reg_iop_sap_out_rw_gio_offset 16
/* Constants */
#define regk_iop_sap_out_always 0x00000001
#define regk_iop_sap_out_and 0x00000002
#define regk_iop_sap_out_clk0 0x00000000
#define regk_iop_sap_out_clk1 0x00000001
#define regk_iop_sap_out_clk12 0x00000004
#define regk_iop_sap_out_clk200 0x00000000
#define regk_iop_sap_out_ext 0x00000002
#define regk_iop_sap_out_gated 0x00000003
#define regk_iop_sap_out_gio0 0x00000000
#define regk_iop_sap_out_gio1 0x00000000
#define regk_iop_sap_out_gio16 0x00000002
#define regk_iop_sap_out_gio17 0x00000002
#define regk_iop_sap_out_gio24 0x00000003
#define regk_iop_sap_out_gio25 0x00000003
#define regk_iop_sap_out_gio8 0x00000001
#define regk_iop_sap_out_gio9 0x00000001
#define regk_iop_sap_out_gio_out10 0x00000005
#define regk_iop_sap_out_gio_out18 0x00000006
#define regk_iop_sap_out_gio_out2 0x00000004
#define regk_iop_sap_out_gio_out26 0x00000007
#define regk_iop_sap_out_inv 0x00000001
#define regk_iop_sap_out_nand 0x00000003
#define regk_iop_sap_out_no 0x00000000
#define regk_iop_sap_out_none 0x00000000
#define regk_iop_sap_out_one 0x00000001
#define regk_iop_sap_out_rw_bus_default 0x00000000
#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000
#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000
#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
#define regk_iop_sap_out_rw_gio_default 0x00000000
#define regk_iop_sap_out_rw_gio_size 0x00000020
#define regk_iop_sap_out_spu_gio6 0x00000002
#define regk_iop_sap_out_spu_gio7 0x00000003
#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000
#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001
#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002
#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003
#define regk_iop_sap_out_tmr200 0x00000001
#define regk_iop_sap_out_yes 0x00000001
#endif /* __iop_sap_out_defs_asm_h */
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