!1085 irqchip/gicv3-its: Add workaround for hip09 ITS erratum 162100801

Merge Pull Request from: @cj-xiaocai 
 
When enabled GICv4.1 in hip09, there are some invalid vPE configurations in
configuration table for some situations, which will cause some vSGI
interrupts lost.
To fix the issue, need to send vinvall command after vmovp.
 
 
Link:https://gitee.com/openeuler/kernel/pulls/1085 

Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> 
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com> 

Documentation/arm64/silicon-errata.rst

@@ -149,6 +149,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Hisilicon      | TSV{110,200}    | #1980005        | HISILICON_ERRATUM_1980005   |
 +----------------+-----------------+-----------------+-----------------------------+
+| Hisilicon      | Hip09           | #162100801      | HISILICON_ERRATUM_162100801 |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 +----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

@@ -802,6 +802,16 @@ config HISILICON_ERRATUM_1980005
 
 	  If unsure, say N.
 
+config HISILICON_ERRATUM_162100801
+    bool "Hip09 162100801 erratum support"
+    default y
+    help
+	When enabled GICv4.1 in hip09, there are some invalid vPE config
+	in configuration tables for some situation, which will cause vSGI
+	interrupts lost. So fix it by sending vinvall commands after vmovp.
+
+	If unsure, say Y.
+
 config QCOM_FALKOR_ERRATUM_1003
 	bool "Falkor E1003: Incorrect translation due to ASID change"
 	default y

arch/arm64/configs/openeuler_defconfig

@@ -390,6 +390,7 @@ CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
 CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
 CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH=y
 # CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF is not set
+CONFIG_HISILICON_ERRATUM_162100801=y
 # end of ARM errata workarounds via the alternatives framework
 
 CONFIG_ARM64_4K_PAGES=y

drivers/irqchip/irq-gic-v3-its.c

@@ -46,6 +46,7 @@
 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
+#define ITS_FLAGS_WORKAROUND_HISILICON_162100801	(1ULL << 3)
 
 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
@@ -1294,6 +1295,14 @@ static void its_send_vmapp(struct its_node *its,
 	its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
 }
 
+static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
+{
+	struct its_cmd_desc desc;
+
+	desc.its_vinvall_cmd.vpe = vpe;
+	its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
+}
+
 static void its_send_vmovp(struct its_vpe *vpe)
 {
 	struct its_cmd_desc desc = {};
@@ -1333,19 +1342,14 @@ static void its_send_vmovp(struct its_vpe *vpe)
 
 		desc.its_vmovp_cmd.col = &its->collections[col_id];
 		its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
+		if (is_v4_1(its) && (its->flags &
+			    ITS_FLAGS_WORKAROUND_HISILICON_162100801))
+			its_send_vinvall(its, vpe);
 	}
 
 	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
 }
 
-static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
-{
-	struct its_cmd_desc desc;
-
-	desc.its_vinvall_cmd.vpe = vpe;
-	its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
-}
-
 static void its_send_vinv(struct its_device *dev, u32 event_id)
 {
 	struct its_cmd_desc desc;
@@ -4967,6 +4971,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
 	return true;
 }
 
+static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data)
+{
+	struct its_node *its = data;
+
+	its->flags |= ITS_FLAGS_WORKAROUND_HISILICON_162100801;
+	return true;
+}
+
 static const struct gic_quirk its_quirks[] = {
 #ifdef CONFIG_CAVIUM_ERRATUM_22375
 	{
@@ -5012,6 +5024,14 @@ static const struct gic_quirk its_quirks[] = {
 		.mask	= 0xffffffff,
 		.init	= its_enable_quirk_hip07_161600802,
 	},
+#endif
+#ifdef CONFIG_HISILICON_ERRATUM_162100801
+	{
+		.desc = "ITS: Hip09 erratum 162100801",
+		.iidr = 0x00051736,
+		.mask = 0xffffffff,
+		.init = its_enable_quirk_hip09_162100801,
+	},
 #endif
 	{
 	}