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提交 50536946 编写于 作者: B Ben Skeggs
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drm/nouveau: store engine type in gpuobj class structs 

We will eventually want to address hw engines other than PGRAPH.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
上级 9100468d
隐藏空白更改
内联 并排
Showing with 127 addition and 127 deletion
drivers/gpu/drm/nouveau/nouveau_drv.h
浏览文件 @ 50536946
...@@ -132,7 +132,7 @@ enum nouveau_flags { ...@@ -132,7 +132,7 @@ enum nouveau_flags {
#define NVOBJ_ENGINE_SW 0 #define NVOBJ_ENGINE_SW 0
#define NVOBJ_ENGINE_GR 1 #define NVOBJ_ENGINE_GR 1
#define NVOBJ_ENGINE_DISPLAY 2 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
#define NVOBJ_ENGINE_INT 0xdeadbeef #define NVOBJ_ENGINE_INT 0xdeadbeef
#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
...@@ -324,7 +324,7 @@ struct nouveau_pgraph_object_method { ...@@ -324,7 +324,7 @@ struct nouveau_pgraph_object_method {
struct nouveau_pgraph_object_class { struct nouveau_pgraph_object_class {
int id; int id;
bool software; u32 engine;
struct nouveau_pgraph_object_method *methods; struct nouveau_pgraph_object_method *methods;
}; };
......
drivers/gpu/drm/nouveau/nouveau_object.c
浏览文件 @ 50536946
...@@ -900,7 +900,7 @@ int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, ...@@ -900,7 +900,7 @@ int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
goto out; goto out;
} }
if (!grc->software) if (grc->engine != NVOBJ_ENGINE_SW)
ret = nouveau_gpuobj_gr_new(chan, grc->id, &gr); ret = nouveau_gpuobj_gr_new(chan, grc->id, &gr);
else else
ret = nouveau_gpuobj_sw_new(chan, grc->id, &gr); ret = nouveau_gpuobj_sw_new(chan, grc->id, &gr);
......
drivers/gpu/drm/nouveau/nv04_graph.c
浏览文件 @ 50536946
...@@ -1091,48 +1091,48 @@ static struct nouveau_pgraph_object_method nv04_graph_mthds_surf3d[] = { ...@@ -1091,48 +1091,48 @@ static struct nouveau_pgraph_object_method nv04_graph_mthds_surf3d[] = {
}; };
struct nouveau_pgraph_object_class nv04_graph_grclass[] = { struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
{ 0x0038, false, NULL }, /* dvd subpicture */ { 0x0038, NVOBJ_ENGINE_GR, NULL }, /* dvd subpicture */
{ 0x0039, false, NULL }, /* m2mf */ { 0x0039, NVOBJ_ENGINE_GR, NULL }, /* m2mf */
{ 0x004b, false, nv04_graph_mthds_nv03_gdirect }, /* nv03 gdirect */ { 0x004b, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv03_gdirect }, /* nv03 gdirect */
{ 0x004a, false, nv04_graph_mthds_nv04_gdirect }, /* nv04 gdirect */ { 0x004a, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_gdirect }, /* nv04 gdirect */
{ 0x001f, false, nv04_graph_mthds_nv01_imageblit }, /* nv01 imageblit */ { 0x001f, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv01_imageblit }, /* nv01 imageblit */
{ 0x005f, false, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 imageblit */ { 0x005f, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 imageblit */
{ 0x0060, false, nv04_graph_mthds_nv04_iifc }, /* nv04 iifc */ { 0x0060, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_iifc }, /* nv04 iifc */
{ 0x0064, false, NULL }, /* nv05 iifc */ { 0x0064, NVOBJ_ENGINE_GR, NULL }, /* nv05 iifc */
{ 0x0021, false, nv04_graph_mthds_nv01_ifc }, /* nv01 ifc */ { 0x0021, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv01_ifc }, /* nv01 ifc */
{ 0x0061, false, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 ifc */ { 0x0061, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 ifc */
{ 0x0065, false, NULL }, /* nv05 ifc */ { 0x0065, NVOBJ_ENGINE_GR, NULL }, /* nv05 ifc */
{ 0x0036, false, nv04_graph_mthds_nv03_sifc }, /* nv03 sifc */ { 0x0036, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv03_sifc }, /* nv03 sifc */
{ 0x0076, false, nv04_graph_mthds_nv04_sifc }, /* nv04 sifc */ { 0x0076, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_sifc }, /* nv04 sifc */
{ 0x0066, false, NULL }, /* nv05 sifc */ { 0x0066, NVOBJ_ENGINE_GR, NULL }, /* nv05 sifc */
{ 0x0037, false, nv04_graph_mthds_nv03_sifm }, /* nv03 sifm */ { 0x0037, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv03_sifm }, /* nv03 sifm */
{ 0x0077, false, nv04_graph_mthds_nv04_sifm }, /* nv04 sifm */ { 0x0077, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_sifm }, /* nv04 sifm */
{ 0x0030, false, NULL }, /* null */ { 0x0030, NVOBJ_ENGINE_GR, NULL }, /* null */
{ 0x0042, false, NULL }, /* surf2d */ { 0x0042, NVOBJ_ENGINE_GR, NULL }, /* surf2d */
{ 0x0043, false, NULL }, /* rop */ { 0x0043, NVOBJ_ENGINE_GR, NULL }, /* rop */
{ 0x0012, false, NULL }, /* beta1 */ { 0x0012, NVOBJ_ENGINE_GR, NULL }, /* beta1 */
{ 0x0072, false, NULL }, /* beta4 */ { 0x0072, NVOBJ_ENGINE_GR, NULL }, /* beta4 */
{ 0x0019, false, NULL }, /* cliprect */ { 0x0019, NVOBJ_ENGINE_GR, NULL }, /* cliprect */
{ 0x0018, false, NULL }, /* nv01 pattern */ { 0x0018, NVOBJ_ENGINE_GR, NULL }, /* nv01 pattern */
{ 0x0044, false, NULL }, /* nv04 pattern */ { 0x0044, NVOBJ_ENGINE_GR, NULL }, /* nv04 pattern */
{ 0x0052, false, NULL }, /* swzsurf */ { 0x0052, NVOBJ_ENGINE_GR, NULL }, /* swzsurf */
{ 0x0053, false, nv04_graph_mthds_surf3d }, /* surf3d */ { 0x0053, NVOBJ_ENGINE_GR, nv04_graph_mthds_surf3d }, /* surf3d */
{ 0x0048, false, nv04_graph_mthds_nv03_tex_tri }, /* nv03 tex_tri */ { 0x0048, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv03_tex_tri }, /* nv03 tex_tri */
{ 0x0054, false, NULL }, /* tex_tri */ { 0x0054, NVOBJ_ENGINE_GR, NULL }, /* tex_tri */
{ 0x0055, false, NULL }, /* multitex_tri */ { 0x0055, NVOBJ_ENGINE_GR, NULL }, /* multitex_tri */
{ 0x0017, false, NULL }, /* nv01 chroma */ { 0x0017, NVOBJ_ENGINE_GR, NULL }, /* nv01 chroma */
{ 0x0057, false, NULL }, /* nv04 chroma */ { 0x0057, NVOBJ_ENGINE_GR, NULL }, /* nv04 chroma */
{ 0x0058, false, NULL }, /* surf_dst */ { 0x0058, NVOBJ_ENGINE_GR, NULL }, /* surf_dst */
{ 0x0059, false, NULL }, /* surf_src */ { 0x0059, NVOBJ_ENGINE_GR, NULL }, /* surf_src */
{ 0x005a, false, NULL }, /* surf_color */ { 0x005a, NVOBJ_ENGINE_GR, NULL }, /* surf_color */
{ 0x005b, false, NULL }, /* surf_zeta */ { 0x005b, NVOBJ_ENGINE_GR, NULL }, /* surf_zeta */
{ 0x001c, false, nv04_graph_mthds_nv01_shape }, /* nv01 line */ { 0x001c, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv01_shape }, /* nv01 line */
{ 0x005c, false, nv04_graph_mthds_nv04_shape }, /* nv04 line */ { 0x005c, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_shape }, /* nv04 line */
{ 0x001d, false, nv04_graph_mthds_nv01_shape }, /* nv01 tri */ { 0x001d, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv01_shape }, /* nv01 tri */
{ 0x005d, false, nv04_graph_mthds_nv04_shape }, /* nv04 tri */ { 0x005d, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_shape }, /* nv04 tri */
{ 0x001e, false, nv04_graph_mthds_nv01_shape }, /* nv01 rect */ { 0x001e, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv01_shape }, /* nv01 rect */
{ 0x005e, false, nv04_graph_mthds_nv04_shape }, /* nv04 rect */ { 0x005e, NVOBJ_ENGINE_GR, nv04_graph_mthds_nv04_shape }, /* nv04 rect */
{ 0x506e, true, nv04_graph_mthds_sw }, { 0x506e, NVOBJ_ENGINE_SW, nv04_graph_mthds_sw },
{} {}
}; };
drivers/gpu/drm/nouveau/nv10_graph.c
浏览文件 @ 50536946
...@@ -1075,25 +1075,25 @@ static struct nouveau_pgraph_object_method nv17_graph_celsius_mthds[] = { ...@@ -1075,25 +1075,25 @@ static struct nouveau_pgraph_object_method nv17_graph_celsius_mthds[] = {
}; };
struct nouveau_pgraph_object_class nv10_graph_grclass[] = { struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
{ 0x0030, false, NULL }, /* null */ { 0x0030, NVOBJ_ENGINE_GR, NULL }, /* null */
{ 0x0039, false, NULL }, /* m2mf */ { 0x0039, NVOBJ_ENGINE_GR, NULL }, /* m2mf */
{ 0x004a, false, NULL }, /* gdirect */ { 0x004a, NVOBJ_ENGINE_GR, NULL }, /* gdirect */
{ 0x005f, false, NULL }, /* imageblit */ { 0x005f, NVOBJ_ENGINE_GR, NULL }, /* imageblit */
{ 0x009f, false, NULL }, /* imageblit (nv12) */ { 0x009f, NVOBJ_ENGINE_GR, NULL }, /* imageblit (nv12) */
{ 0x008a, false, NULL }, /* ifc */ { 0x008a, NVOBJ_ENGINE_GR, NULL }, /* ifc */
{ 0x0089, false, NULL }, /* sifm */ { 0x0089, NVOBJ_ENGINE_GR, NULL }, /* sifm */
{ 0x0062, false, NULL }, /* surf2d */ { 0x0062, NVOBJ_ENGINE_GR, NULL }, /* surf2d */
{ 0x0043, false, NULL }, /* rop */ { 0x0043, NVOBJ_ENGINE_GR, NULL }, /* rop */
{ 0x0012, false, NULL }, /* beta1 */ { 0x0012, NVOBJ_ENGINE_GR, NULL }, /* beta1 */
{ 0x0072, false, NULL }, /* beta4 */ { 0x0072, NVOBJ_ENGINE_GR, NULL }, /* beta4 */
{ 0x0019, false, NULL }, /* cliprect */ { 0x0019, NVOBJ_ENGINE_GR, NULL }, /* cliprect */
{ 0x0044, false, NULL }, /* pattern */ { 0x0044, NVOBJ_ENGINE_GR, NULL }, /* pattern */
{ 0x0052, false, NULL }, /* swzsurf */ { 0x0052, NVOBJ_ENGINE_GR, NULL }, /* swzsurf */
{ 0x0093, false, NULL }, /* surf3d */ { 0x0093, NVOBJ_ENGINE_GR, NULL }, /* surf3d */
{ 0x0094, false, NULL }, /* tex_tri */ { 0x0094, NVOBJ_ENGINE_GR, NULL }, /* tex_tri */
{ 0x0095, false, NULL }, /* multitex_tri */ { 0x0095, NVOBJ_ENGINE_GR, NULL }, /* multitex_tri */
{ 0x0056, false, NULL }, /* celcius (nv10) */ { 0x0056, NVOBJ_ENGINE_GR, NULL }, /* celcius (nv10) */
{ 0x0096, false, NULL }, /* celcius (nv11) */ { 0x0096, NVOBJ_ENGINE_GR, NULL }, /* celcius (nv11) */
{ 0x0099, false, nv17_graph_celsius_mthds }, /* celcius (nv17) */ { 0x0099, NVOBJ_ENGINE_GR, nv17_graph_celsius_mthds }, /* celcius (nv17) */
{} {}
}; };
drivers/gpu/drm/nouveau/nv20_graph.c
浏览文件 @ 50536946
...@@ -757,45 +757,45 @@ nv30_graph_init(struct drm_device *dev) ...@@ -757,45 +757,45 @@ nv30_graph_init(struct drm_device *dev)
} }
struct nouveau_pgraph_object_class nv20_graph_grclass[] = { struct nouveau_pgraph_object_class nv20_graph_grclass[] = {
{ 0x0030, false, NULL }, /* null */ { 0x0030, NVOBJ_ENGINE_GR, NULL }, /* null */
{ 0x0039, false, NULL }, /* m2mf */ { 0x0039, NVOBJ_ENGINE_GR, NULL }, /* m2mf */
{ 0x004a, false, NULL }, /* gdirect */ { 0x004a, NVOBJ_ENGINE_GR, NULL }, /* gdirect */
{ 0x009f, false, NULL }, /* imageblit (nv12) */ { 0x009f, NVOBJ_ENGINE_GR, NULL }, /* imageblit (nv12) */
{ 0x008a, false, NULL }, /* ifc */ { 0x008a, NVOBJ_ENGINE_GR, NULL }, /* ifc */
{ 0x0089, false, NULL }, /* sifm */ { 0x0089, NVOBJ_ENGINE_GR, NULL }, /* sifm */
{ 0x0062, false, NULL }, /* surf2d */ { 0x0062, NVOBJ_ENGINE_GR, NULL }, /* surf2d */
{ 0x0043, false, NULL }, /* rop */ { 0x0043, NVOBJ_ENGINE_GR, NULL }, /* rop */
{ 0x0012, false, NULL }, /* beta1 */ { 0x0012, NVOBJ_ENGINE_GR, NULL }, /* beta1 */
{ 0x0072, false, NULL }, /* beta4 */ { 0x0072, NVOBJ_ENGINE_GR, NULL }, /* beta4 */
{ 0x0019, false, NULL }, /* cliprect */ { 0x0019, NVOBJ_ENGINE_GR, NULL }, /* cliprect */
{ 0x0044, false, NULL }, /* pattern */ { 0x0044, NVOBJ_ENGINE_GR, NULL }, /* pattern */
{ 0x009e, false, NULL }, /* swzsurf */ { 0x009e, NVOBJ_ENGINE_GR, NULL }, /* swzsurf */
{ 0x0096, false, NULL }, /* celcius */ { 0x0096, NVOBJ_ENGINE_GR, NULL }, /* celcius */
{ 0x0097, false, NULL }, /* kelvin (nv20) */ { 0x0097, NVOBJ_ENGINE_GR, NULL }, /* kelvin (nv20) */
{ 0x0597, false, NULL }, /* kelvin (nv25) */ { 0x0597, NVOBJ_ENGINE_GR, NULL }, /* kelvin (nv25) */
{} {}
}; };
struct nouveau_pgraph_object_class nv30_graph_grclass[] = { struct nouveau_pgraph_object_class nv30_graph_grclass[] = {
{ 0x0030, false, NULL }, /* null */ { 0x0030, NVOBJ_ENGINE_GR, NULL }, /* null */
{ 0x0039, false, NULL }, /* m2mf */ { 0x0039, NVOBJ_ENGINE_GR, NULL }, /* m2mf */
{ 0x004a, false, NULL }, /* gdirect */ { 0x004a, NVOBJ_ENGINE_GR, NULL }, /* gdirect */
{ 0x009f, false, NULL }, /* imageblit (nv12) */ { 0x009f, NVOBJ_ENGINE_GR, NULL }, /* imageblit (nv12) */
{ 0x008a, false, NULL }, /* ifc */ { 0x008a, NVOBJ_ENGINE_GR, NULL }, /* ifc */
{ 0x038a, false, NULL }, /* ifc (nv30) */ { 0x038a, NVOBJ_ENGINE_GR, NULL }, /* ifc (nv30) */
{ 0x0089, false, NULL }, /* sifm */ { 0x0089, NVOBJ_ENGINE_GR, NULL }, /* sifm */
{ 0x0389, false, NULL }, /* sifm (nv30) */ { 0x0389, NVOBJ_ENGINE_GR, NULL }, /* sifm (nv30) */
{ 0x0062, false, NULL }, /* surf2d */ { 0x0062, NVOBJ_ENGINE_GR, NULL }, /* surf2d */
{ 0x0362, false, NULL }, /* surf2d (nv30) */ { 0x0362, NVOBJ_ENGINE_GR, NULL }, /* surf2d (nv30) */
{ 0x0043, false, NULL }, /* rop */ { 0x0043, NVOBJ_ENGINE_GR, NULL }, /* rop */
{ 0x0012, false, NULL }, /* beta1 */ { 0x0012, NVOBJ_ENGINE_GR, NULL }, /* beta1 */
{ 0x0072, false, NULL }, /* beta4 */ { 0x0072, NVOBJ_ENGINE_GR, NULL }, /* beta4 */
{ 0x0019, false, NULL }, /* cliprect */ { 0x0019, NVOBJ_ENGINE_GR, NULL }, /* cliprect */
{ 0x0044, false, NULL }, /* pattern */ { 0x0044, NVOBJ_ENGINE_GR, NULL }, /* pattern */
{ 0x039e, false, NULL }, /* swzsurf */ { 0x039e, NVOBJ_ENGINE_GR, NULL }, /* swzsurf */
{ 0x0397, false, NULL }, /* rankine (nv30) */ { 0x0397, NVOBJ_ENGINE_GR, NULL }, /* rankine (nv30) */
{ 0x0497, false, NULL }, /* rankine (nv35) */ { 0x0497, NVOBJ_ENGINE_GR, NULL }, /* rankine (nv35) */
{ 0x0697, false, NULL }, /* rankine (nv34) */ { 0x0697, NVOBJ_ENGINE_GR, NULL }, /* rankine (nv34) */
{} {}
}; };
drivers/gpu/drm/nouveau/nv40_graph.c
浏览文件 @ 50536946
...@@ -409,23 +409,23 @@ void nv40_graph_takedown(struct drm_device *dev) ...@@ -409,23 +409,23 @@ void nv40_graph_takedown(struct drm_device *dev)
} }
struct nouveau_pgraph_object_class nv40_graph_grclass[] = { struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
{ 0x0030, false, NULL }, /* null */ { 0x0030, NVOBJ_ENGINE_GR, NULL }, /* null */
{ 0x0039, false, NULL }, /* m2mf */ { 0x0039, NVOBJ_ENGINE_GR, NULL }, /* m2mf */
{ 0x004a, false, NULL }, /* gdirect */ { 0x004a, NVOBJ_ENGINE_GR, NULL }, /* gdirect */
{ 0x009f, false, NULL }, /* imageblit (nv12) */ { 0x009f, NVOBJ_ENGINE_GR, NULL }, /* imageblit (nv12) */
{ 0x008a, false, NULL }, /* ifc */ { 0x008a, NVOBJ_ENGINE_GR, NULL }, /* ifc */
{ 0x0089, false, NULL }, /* sifm */ { 0x0089, NVOBJ_ENGINE_GR, NULL }, /* sifm */
{ 0x3089, false, NULL }, /* sifm (nv40) */ { 0x3089, NVOBJ_ENGINE_GR, NULL }, /* sifm (nv40) */
{ 0x0062, false, NULL }, /* surf2d */ { 0x0062, NVOBJ_ENGINE_GR, NULL }, /* surf2d */
{ 0x3062, false, NULL }, /* surf2d (nv40) */ { 0x3062, NVOBJ_ENGINE_GR, NULL }, /* surf2d (nv40) */
{ 0x0043, false, NULL }, /* rop */ { 0x0043, NVOBJ_ENGINE_GR, NULL }, /* rop */
{ 0x0012, false, NULL }, /* beta1 */ { 0x0012, NVOBJ_ENGINE_GR, NULL }, /* beta1 */
{ 0x0072, false, NULL }, /* beta4 */ { 0x0072, NVOBJ_ENGINE_GR, NULL }, /* beta4 */
{ 0x0019, false, NULL }, /* cliprect */ { 0x0019, NVOBJ_ENGINE_GR, NULL }, /* cliprect */
{ 0x0044, false, NULL }, /* pattern */ { 0x0044, NVOBJ_ENGINE_GR, NULL }, /* pattern */
{ 0x309e, false, NULL }, /* swzsurf */ { 0x309e, NVOBJ_ENGINE_GR, NULL }, /* swzsurf */
{ 0x4097, false, NULL }, /* curie (nv40) */ { 0x4097, NVOBJ_ENGINE_GR, NULL }, /* curie (nv40) */
{ 0x4497, false, NULL }, /* curie (nv44) */ { 0x4497, NVOBJ_ENGINE_GR, NULL }, /* curie (nv44) */
{} {}
}; };
drivers/gpu/drm/nouveau/nv50_graph.c
浏览文件 @ 50536946
...@@ -401,16 +401,16 @@ static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = { ...@@ -401,16 +401,16 @@ static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = {
}; };
struct nouveau_pgraph_object_class nv50_graph_grclass[] = { struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
{ 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */ { 0x506e, NVOBJ_ENGINE_SW, nv50_graph_nvsw_methods }, /* nvsw */
{ 0x0030, false, NULL }, /* null */ { 0x0030, NVOBJ_ENGINE_GR, NULL }, /* null */
{ 0x5039, false, NULL }, /* m2mf */ { 0x5039, NVOBJ_ENGINE_GR, NULL }, /* m2mf */
{ 0x502d, false, NULL }, /* 2d */ { 0x502d, NVOBJ_ENGINE_GR, NULL }, /* 2d */
{ 0x50c0, false, NULL }, /* compute */ { 0x50c0, NVOBJ_ENGINE_GR, NULL }, /* compute */
{ 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */ { 0x85c0, NVOBJ_ENGINE_GR, NULL }, /* compute (nva3, nva5, nva8) */
{ 0x5097, false, NULL }, /* tesla (nv50) */ { 0x5097, NVOBJ_ENGINE_GR, NULL }, /* tesla (nv50) */
{ 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */ { 0x8297, NVOBJ_ENGINE_GR, NULL }, /* tesla (nv8x/nv9x) */
{ 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */ { 0x8397, NVOBJ_ENGINE_GR, NULL }, /* tesla (nva0, nvaa, nvac) */
{ 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */ { 0x8597, NVOBJ_ENGINE_GR, NULL }, /* tesla (nva3, nva5, nva8) */
{} {}
}; };
......
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