xhci: fix issue of cross page boundary in TRB prefetch

zhaoxin inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I40QDN
CVE: NA

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On some Zhaoxin platforms, xHCI will prefetch TRB for performance
improvement. However this TRB prefetch mechanism may cross page boundary,
which may access memory not belong to xHCI. In order to fix this issue,
using two pages for TRB allocate and only the first page will be used.
Signed-off-by: NLeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
Reviewed-by: NHanjun Guo <guohanjun@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>

drivers/usb/host/xhci-mem.c

@@ -2458,8 +2458,16 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
 	 * and our use of dma addresses in the trb_address_map radix tree needs
 	 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
 	 */
-	xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
+	/* With xHCI TRB prefetch patch:To fix cross page boundary access issue
+	 * in IOV environment
+	 */
+	if (xhci->quirks & XHCI_ZHAOXIN_TRB_FETCH) {
+		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
+			TRB_SEGMENT_SIZE*2, TRB_SEGMENT_SIZE*2, xhci->page_size*2);
+	} else {
+		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
 			TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
+	}
 
 	/* See Table 46 and Note on Figure 55 */
 	xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,

drivers/usb/host/xhci-pci.c

@@ -281,6 +281,11 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 	if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
 		xhci->quirks |= XHCI_LPM_SUPPORT;
 
+	if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN &&
+		(pdev->device == 0x9202 ||
+		 pdev->device == 0x9203))
+		xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
+
 	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 		xhci->quirks |= XHCI_BROKEN_STREAMS;

drivers/usb/host/xhci.h

@@ -1881,6 +1881,7 @@ struct xhci_hcd {
 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK	BIT_ULL(39)
 #define XHCI_NO_SOFT_RETRY	BIT_ULL(40)
 #define XHCI_ZHAOXIN_HOST	BIT_ULL(41)
+#define XHCI_ZHAOXIN_TRB_FETCH	BIT_ULL(42)
 
 	unsigned int		num_active_eps;
 	unsigned int		limit_active_eps;