drm/nouveau/disp/nv50-: add channel interfaces to determine the user area

This will be required to support Volta.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c

@@ -155,13 +155,20 @@ nv50_disp_chan_uevent = {
 	.fini = nv50_disp_chan_uevent_fini,
 };
 
+u64
+nv50_disp_chan_user(struct nv50_disp_chan *chan, u64 *psize)
+{
+	*psize = 0x1000;
+	return 0x640000 + (chan->chid.user * 0x1000);
+}
+
 static int
 nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr, u32 *data)
 {
 	struct nv50_disp_chan *chan = nv50_disp_chan(object);
-	struct nv50_disp *disp = chan->disp;
-	struct nvkm_device *device = disp->base.engine.subdev.device;
-	*data = nvkm_rd32(device, 0x640000 + (chan->chid.user * 0x1000) + addr);
+	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
+	u64 size, base = chan->func->user(chan, &size);
+	*data = nvkm_rd32(device, base + addr);
 	return 0;
 }
 
@@ -169,9 +176,9 @@ static int
 nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data)
 {
 	struct nv50_disp_chan *chan = nv50_disp_chan(object);
-	struct nv50_disp *disp = chan->disp;
-	struct nvkm_device *device = disp->base.engine.subdev.device;
-	nvkm_wr32(device, 0x640000 + (chan->chid.user * 0x1000) + addr, data);
+	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
+	u64 size, base = chan->func->user(chan, &size);
+	nvkm_wr32(device, base + addr, data);
 	return 0;
 }
 
@@ -196,12 +203,10 @@ nv50_disp_chan_map(struct nvkm_object *object, void *argv, u32 argc,
 		   enum nvkm_object_map *type, u64 *addr, u64 *size)
 {
 	struct nv50_disp_chan *chan = nv50_disp_chan(object);
-	struct nv50_disp *disp = chan->disp;
-	struct nvkm_device *device = disp->base.engine.subdev.device;
+	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
+	const u64 base = device->func->resource_addr(device, 0);
 	*type = NVKM_OBJECT_MAP_IO;
-	*addr = device->func->resource_addr(device, 0) +
-		0x640000 + (chan->chid.user * 0x1000);
-	*size = 0x001000;
+	*addr = base + chan->func->user(chan, size);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h

@@ -25,6 +25,7 @@ struct nv50_disp_chan {
 struct nv50_disp_chan_func {
 	int (*init)(struct nv50_disp_chan *);
 	void (*fini)(struct nv50_disp_chan *);
+	u64 (*user)(struct nv50_disp_chan *, u64 *size);
 	int (*bind)(struct nv50_disp_chan *, struct nvkm_object *, u32 handle);
 };
 
@@ -37,6 +38,7 @@ int nv50_disp_dmac_new_(const struct nv50_disp_chan_func *,
 			struct nv50_disp *, int chid, int head, u64 push,
 			const struct nvkm_oclass *, struct nvkm_object **);
 
+u64 nv50_disp_chan_user(struct nv50_disp_chan *, u64 *);
 extern const struct nv50_disp_chan_func nv50_disp_pioc_func;
 extern const struct nv50_disp_chan_func nv50_disp_dmac_func;
 int nv50_disp_dmac_bind(struct nv50_disp_chan *, struct nvkm_object *, u32);

drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c

@@ -222,6 +222,7 @@ const struct nv50_disp_chan_func
 gf119_disp_core_func = {
 	.init = gf119_disp_core_init,
 	.fini = gf119_disp_core_fini,
+	.user = nv50_disp_chan_user,
 	.bind = gf119_disp_dmac_bind,
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c

@@ -59,6 +59,7 @@ static const struct nv50_disp_chan_func
 gp102_disp_core_func = {
 	.init = gp102_disp_core_init,
 	.fini = gf119_disp_core_fini,
+	.user = nv50_disp_chan_user,
 	.bind = gf119_disp_dmac_bind,
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c

@@ -224,6 +224,7 @@ const struct nv50_disp_chan_func
 nv50_disp_core_func = {
 	.init = nv50_disp_core_init,
 	.fini = nv50_disp_core_fini,
+	.user = nv50_disp_chan_user,
 	.bind = nv50_disp_dmac_bind,
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c

@@ -95,5 +95,6 @@ const struct nv50_disp_chan_func
 gf119_disp_dmac_func = {
 	.init = gf119_disp_dmac_init,
 	.fini = gf119_disp_dmac_fini,
+	.user = nv50_disp_chan_user,
 	.bind = gf119_disp_dmac_bind,
 };

drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c

@@ -61,5 +61,6 @@ const struct nv50_disp_chan_func
 gp102_disp_dmac_func = {
 	.init = gp102_disp_dmac_init,
 	.fini = gf119_disp_dmac_fini,
+	.user = nv50_disp_chan_user,
 	.bind = gf119_disp_dmac_bind,
 };

drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c

@@ -137,5 +137,6 @@ const struct nv50_disp_chan_func
 nv50_disp_dmac_func = {
 	.init = nv50_disp_dmac_init,
 	.fini = nv50_disp_dmac_fini,
+	.user = nv50_disp_chan_user,
 	.bind = nv50_disp_dmac_bind,
 };

drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c

@@ -80,4 +80,5 @@ const struct nv50_disp_chan_func
 gf119_disp_pioc_func = {
 	.init = gf119_disp_pioc_init,
 	.fini = gf119_disp_pioc_fini,
+	.user = nv50_disp_chan_user,
 };

drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c

@@ -82,4 +82,5 @@ const struct nv50_disp_chan_func
 nv50_disp_pioc_func = {
 	.init = nv50_disp_pioc_init,
 	.fini = nv50_disp_pioc_fini,
+	.user = nv50_disp_chan_user,
 };