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提交 458e6a51 编写于 作者: F Felipe Balbi 提交者： Greg Kroah-Hartman
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usb: musb: general cleanup to musbhsdma.c 

Basically getting rid of CaMeLcAsE, but also adding
missing lines and spaces.
Signed-off-by: NFelipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 c767c1c6
隐藏空白更改
内联 并排
Showing with 155 addition and 151 deletion
drivers/usb/musb/musbhsdma.c
浏览文件 @ 458e6a51
...@@ -45,8 +45,8 @@ ...@@ -45,8 +45,8 @@
#define MUSB_HSDMA_ADDRESS 0x8 #define MUSB_HSDMA_ADDRESS 0x8
#define MUSB_HSDMA_COUNT 0xc #define MUSB_HSDMA_COUNT 0xc
#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \ #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
(MUSB_HSDMA_BASE + (_bChannel << 4) + _offset) (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
/* control register (16-bit): */ /* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT 0 #define MUSB_HSDMA_ENABLE_SHIFT 0
...@@ -67,23 +67,23 @@ ...@@ -67,23 +67,23 @@
struct musb_dma_controller; struct musb_dma_controller;
struct musb_dma_channel { struct musb_dma_channel {
struct dma_channel Channel; struct dma_channel channel;
struct musb_dma_controller *controller; struct musb_dma_controller *controller;
u32 dwStartAddress; u32 start_addr;
u32 len; u32 len;
u16 wMaxPacketSize; u16 max_packet_sz;
u8 bIndex; u8 idx;
u8 epnum; u8 epnum;
u8 transmit; u8 transmit;
}; };
struct musb_dma_controller { struct musb_dma_controller {
struct dma_controller Controller; struct dma_controller controller;
struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS]; struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
void *pDmaPrivate; void *private_data;
void __iomem *pCoreBase; void __iomem *base;
u8 bChannelCount; u8 channel_count;
u8 bmUsedChannels; u8 used_channels;
u8 irq; u8 irq;
}; };
...@@ -93,91 +93,91 @@ static int dma_controller_start(struct dma_controller *c) ...@@ -93,91 +93,91 @@ static int dma_controller_start(struct dma_controller *c)
return 0; return 0;
} }
static void dma_channel_release(struct dma_channel *pChannel); static void dma_channel_release(struct dma_channel *channel);
static int dma_controller_stop(struct dma_controller *c) static int dma_controller_stop(struct dma_controller *c)
{ {
struct musb_dma_controller *controller = struct musb_dma_controller *controller = container_of(c,
container_of(c, struct musb_dma_controller, Controller); struct musb_dma_controller, controller);
struct musb *musb = (struct musb *) controller->pDmaPrivate; struct musb *musb = controller->private_data;
struct dma_channel *pChannel; struct dma_channel *channel;
u8 bBit; u8 bit;
if (controller->bmUsedChannels != 0) { if (controller->used_channels != 0) {
dev_err(musb->controller, dev_err(musb->controller,
"Stopping DMA controller while channel active\n"); "Stopping DMA controller while channel active\n");
for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) { for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
if (controller->bmUsedChannels & (1 << bBit)) { if (controller->used_channels & (1 << bit)) {
pChannel = &controller->aChannel[bBit].Channel; channel = &controller->channel[bit].channel;
dma_channel_release(pChannel); dma_channel_release(channel);
if (!controller->bmUsedChannels) if (!controller->used_channels)
break; break;
} }
} }
} }
return 0; return 0;
} }
static struct dma_channel *dma_channel_allocate(struct dma_controller *c, static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
struct musb_hw_ep *hw_ep, u8 transmit) struct musb_hw_ep *hw_ep, u8 transmit)
{ {
u8 bBit; struct musb_dma_controller *controller = container_of(c,
struct dma_channel *pChannel = NULL; struct musb_dma_controller, controller);
struct musb_dma_channel *pImplChannel = NULL; struct musb_dma_channel *musb_channel = NULL;
struct musb_dma_controller *controller = struct dma_channel *channel = NULL;
container_of(c, struct musb_dma_controller, Controller); u8 bit;
for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) { for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
if (!(controller->bmUsedChannels & (1 << bBit))) { if (!(controller->used_channels & (1 << bit))) {
controller->bmUsedChannels |= (1 << bBit); controller->used_channels |= (1 << bit);
pImplChannel = &(controller->aChannel[bBit]); musb_channel = &(controller->channel[bit]);
pImplChannel->controller = controller; musb_channel->controller = controller;
pImplChannel->bIndex = bBit; musb_channel->idx = bit;
pImplChannel->epnum = hw_ep->epnum; musb_channel->epnum = hw_ep->epnum;
pImplChannel->transmit = transmit; musb_channel->transmit = transmit;
pChannel = &(pImplChannel->Channel); channel = &(musb_channel->channel);
pChannel->private_data = pImplChannel; channel->private_data = musb_channel;
pChannel->status = MUSB_DMA_STATUS_FREE; channel->status = MUSB_DMA_STATUS_FREE;
pChannel->max_len = 0x10000; channel->max_len = 0x10000;
/* Tx => mode 1; Rx => mode 0 */ /* Tx => mode 1; Rx => mode 0 */
pChannel->desired_mode = transmit; channel->desired_mode = transmit;
pChannel->actual_len = 0; channel->actual_len = 0;
break; break;
} }
} }
return pChannel;
return channel;
} }
static void dma_channel_release(struct dma_channel *pChannel) static void dma_channel_release(struct dma_channel *channel)
{ {
struct musb_dma_channel *pImplChannel = struct musb_dma_channel *musb_channel = channel->private_data;
(struct musb_dma_channel *) pChannel->private_data;
pChannel->actual_len = 0; channel->actual_len = 0;
pImplChannel->dwStartAddress = 0; musb_channel->start_addr = 0;
pImplChannel->len = 0; musb_channel->len = 0;
pImplChannel->controller->bmUsedChannels &= musb_channel->controller->used_channels &=
~(1 << pImplChannel->bIndex); ~(1 << musb_channel->idx);
pChannel->status = MUSB_DMA_STATUS_UNKNOWN; channel->status = MUSB_DMA_STATUS_UNKNOWN;
} }
static void configure_channel(struct dma_channel *pChannel, static void configure_channel(struct dma_channel *channel,
u16 packet_sz, u8 mode, u16 packet_sz, u8 mode,
dma_addr_t dma_addr, u32 len) dma_addr_t dma_addr, u32 len)
{ {
struct musb_dma_channel *pImplChannel = struct musb_dma_channel *musb_channel = channel->private_data;
(struct musb_dma_channel *) pChannel->private_data; struct musb_dma_controller *controller = musb_channel->controller;
struct musb_dma_controller *controller = pImplChannel->controller; void __iomem *mbase = controller->base;
void __iomem *mbase = controller->pCoreBase; u8 bchannel = musb_channel->idx;
u8 bChannel = pImplChannel->bIndex;
u16 csr = 0; u16 csr = 0;
DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
pChannel, packet_sz, dma_addr, len, mode); channel, packet_sz, dma_addr, len, mode);
if (mode) { if (mode) {
csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
...@@ -195,180 +195,183 @@ static void configure_channel(struct dma_channel *pChannel, ...@@ -195,180 +195,183 @@ static void configure_channel(struct dma_channel *pChannel,
} }
} }
csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
| (1 << MUSB_HSDMA_ENABLE_SHIFT) | (1 << MUSB_HSDMA_ENABLE_SHIFT)
| (1 << MUSB_HSDMA_IRQENABLE_SHIFT) | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
| (pImplChannel->transmit | (musb_channel->transmit
? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
: 0); : 0);
/* address/count */ /* address/count */
musb_writel(mbase, musb_writel(mbase,
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
dma_addr); dma_addr);
musb_writel(mbase, musb_writel(mbase,
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
len); len);
/* control (this should start things) */ /* control (this should start things) */
musb_writew(mbase, musb_writew(mbase,
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
csr); csr);
} }
static int dma_channel_program(struct dma_channel *pChannel, static int dma_channel_program(struct dma_channel *channel,
u16 packet_sz, u8 mode, u16 packet_sz, u8 mode,
dma_addr_t dma_addr, u32 len) dma_addr_t dma_addr, u32 len)
{ {
struct musb_dma_channel *pImplChannel = struct musb_dma_channel *musb_channel = channel->private_data;
(struct musb_dma_channel *) pChannel->private_data;
DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
pImplChannel->epnum, musb_channel->epnum,
pImplChannel->transmit ? "Tx" : "Rx", musb_channel->transmit ? "Tx" : "Rx",
packet_sz, dma_addr, len, mode); packet_sz, dma_addr, len, mode);
BUG_ON(pChannel->status == MUSB_DMA_STATUS_UNKNOWN || BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
pChannel->status == MUSB_DMA_STATUS_BUSY); channel->status == MUSB_DMA_STATUS_BUSY);
pChannel->actual_len = 0; channel->actual_len = 0;
pImplChannel->dwStartAddress = dma_addr; musb_channel->start_addr = dma_addr;
pImplChannel->len = len; musb_channel->len = len;
pImplChannel->wMaxPacketSize = packet_sz; musb_channel->max_packet_sz = packet_sz;
pChannel->status = MUSB_DMA_STATUS_BUSY; channel->status = MUSB_DMA_STATUS_BUSY;
if ((mode == 1) && (len >= packet_sz)) if ((mode == 1) && (len >= packet_sz))
configure_channel(pChannel, packet_sz, 1, dma_addr, len); configure_channel(channel, packet_sz, 1, dma_addr, len);
else else
configure_channel(pChannel, packet_sz, 0, dma_addr, len); configure_channel(channel, packet_sz, 0, dma_addr, len);
return true; return true;
} }
static int dma_channel_abort(struct dma_channel *pChannel) static int dma_channel_abort(struct dma_channel *channel)
{ {
struct musb_dma_channel *pImplChannel = struct musb_dma_channel *musb_channel = channel->private_data;
(struct musb_dma_channel *) pChannel->private_data; void __iomem *mbase = musb_channel->controller->base;
u8 bChannel = pImplChannel->bIndex;
void __iomem *mbase = pImplChannel->controller->pCoreBase; u8 bchannel = musb_channel->idx;
u16 csr; u16 csr;
if (pChannel->status == MUSB_DMA_STATUS_BUSY) { if (channel->status == MUSB_DMA_STATUS_BUSY) {
if (pImplChannel->transmit) { if (musb_channel->transmit) {
csr = musb_readw(mbase, csr = musb_readw(mbase,
MUSB_EP_OFFSET(pImplChannel->epnum, MUSB_EP_OFFSET(musb_channel->epnum,
MUSB_TXCSR)); MUSB_TXCSR));
csr &= ~(MUSB_TXCSR_AUTOSET | csr &= ~(MUSB_TXCSR_AUTOSET |
MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAENAB |
MUSB_TXCSR_DMAMODE); MUSB_TXCSR_DMAMODE);
musb_writew(mbase, musb_writew(mbase,
MUSB_EP_OFFSET(pImplChannel->epnum, MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
MUSB_TXCSR),
csr); csr);
} else { } else {
csr = musb_readw(mbase, csr = musb_readw(mbase,
MUSB_EP_OFFSET(pImplChannel->epnum, MUSB_EP_OFFSET(musb_channel->epnum,
MUSB_RXCSR)); MUSB_RXCSR));
csr &= ~(MUSB_RXCSR_AUTOCLEAR | csr &= ~(MUSB_RXCSR_AUTOCLEAR |
MUSB_RXCSR_DMAENAB | MUSB_RXCSR_DMAENAB |
MUSB_RXCSR_DMAMODE); MUSB_RXCSR_DMAMODE);
musb_writew(mbase, musb_writew(mbase,
MUSB_EP_OFFSET(pImplChannel->epnum, MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
MUSB_RXCSR),
csr); csr);
} }
musb_writew(mbase, musb_writew(mbase,
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
0); 0);
musb_writel(mbase, musb_writel(mbase,
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
0); 0);
musb_writel(mbase, musb_writel(mbase,
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
0); 0);
pChannel->status = MUSB_DMA_STATUS_FREE; channel->status = MUSB_DMA_STATUS_FREE;
} }
return 0; return 0;
} }
static irqreturn_t dma_controller_irq(int irq, void *private_data) static irqreturn_t dma_controller_irq(int irq, void *private_data)
{ {
struct musb_dma_controller *controller = struct musb_dma_controller *controller = private_data;
(struct musb_dma_controller *)private_data; struct musb *musb = controller->private_data;
struct musb_dma_channel *pImplChannel; struct musb_dma_channel *musb_channel;
struct musb *musb = controller->pDmaPrivate; struct dma_channel *channel;
void __iomem *mbase = controller->pCoreBase;
struct dma_channel *pChannel; void __iomem *mbase = controller->base;
u8 bChannel;
u16 csr;
u32 dwAddress;
u8 int_hsdma;
irqreturn_t retval = IRQ_NONE; irqreturn_t retval = IRQ_NONE;
unsigned long flags; unsigned long flags;
u8 bchannel;
u8 int_hsdma;
u32 addr;
u16 csr;
spin_lock_irqsave(&musb->lock, flags); spin_lock_irqsave(&musb->lock, flags);
int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
if (!int_hsdma) if (!int_hsdma)
goto done; goto done;
for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) { for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
if (int_hsdma & (1 << bChannel)) { if (int_hsdma & (1 << bchannel)) {
pImplChannel = (struct musb_dma_channel *) musb_channel = (struct musb_dma_channel *)
&(controller->aChannel[bChannel]); &(controller->channel[bchannel]);
pChannel = &pImplChannel->Channel; channel = &musb_channel->channel;
csr = musb_readw(mbase, csr = musb_readw(mbase,
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
MUSB_HSDMA_CONTROL)); MUSB_HSDMA_CONTROL));
if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
pImplChannel->Channel.status = musb_channel->channel.status =
MUSB_DMA_STATUS_BUS_ABORT; MUSB_DMA_STATUS_BUS_ABORT;
else { } else {
u8 devctl; u8 devctl;
dwAddress = musb_readl(mbase, addr = musb_readl(mbase,
MUSB_HSDMA_CHANNEL_OFFSET( MUSB_HSDMA_CHANNEL_OFFSET(
bChannel, bchannel,
MUSB_HSDMA_ADDRESS)); MUSB_HSDMA_ADDRESS));
pChannel->actual_len = dwAddress channel->actual_len = addr
- pImplChannel->dwStartAddress; - musb_channel->start_addr;
DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
pChannel, pImplChannel->dwStartAddress, channel, musb_channel->start_addr,
dwAddress, pChannel->actual_len, addr, channel->actual_len,
pImplChannel->len, musb_channel->len,
(pChannel->actual_len (channel->actual_len
< pImplChannel->len) ? < musb_channel->len) ?
"=> reconfig 0" : "=> complete"); "=> reconfig 0" : "=> complete");
devctl = musb_readb(mbase, MUSB_DEVCTL); devctl = musb_readb(mbase, MUSB_DEVCTL);
pChannel->status = MUSB_DMA_STATUS_FREE; channel->status = MUSB_DMA_STATUS_FREE;
/* completed */ /* completed */
if ((devctl & MUSB_DEVCTL_HM) if ((devctl & MUSB_DEVCTL_HM)
&& (pImplChannel->transmit) && (musb_channel->transmit)
&& ((pChannel->desired_mode == 0) && ((channel->desired_mode == 0)
|| (pChannel->actual_len & || (channel->actual_len &
(pImplChannel->wMaxPacketSize - 1))) (musb_channel->max_packet_sz - 1)))
) { ) {
/* Send out the packet */ /* Send out the packet */
musb_ep_select(mbase, musb_ep_select(mbase,
pImplChannel->epnum); musb_channel->epnum);
musb_writew(mbase, MUSB_EP_OFFSET( musb_writew(mbase, MUSB_EP_OFFSET(
pImplChannel->epnum, musb_channel->epnum,
MUSB_TXCSR), MUSB_TXCSR),
MUSB_TXCSR_TXPKTRDY); MUSB_TXCSR_TXPKTRDY);
} else } else {
musb_dma_completion( musb_dma_completion(
musb, musb,
pImplChannel->epnum, musb_channel->epnum,
pImplChannel->transmit); musb_channel->transmit);
}
} }
} }
} }
...@@ -380,9 +383,9 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data) ...@@ -380,9 +383,9 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
void dma_controller_destroy(struct dma_controller *c) void dma_controller_destroy(struct dma_controller *c)
{ {
struct musb_dma_controller *controller; struct musb_dma_controller *controller = container_of(c,
struct musb_dma_controller, controller);
controller = container_of(c, struct musb_dma_controller, Controller);
if (!controller) if (!controller)
return; return;
...@@ -393,7 +396,7 @@ void dma_controller_destroy(struct dma_controller *c) ...@@ -393,7 +396,7 @@ void dma_controller_destroy(struct dma_controller *c)
} }
struct dma_controller *__init struct dma_controller *__init
dma_controller_create(struct musb *musb, void __iomem *pCoreBase) dma_controller_create(struct musb *musb, void __iomem *base)
{ {
struct musb_dma_controller *controller; struct musb_dma_controller *controller;
struct device *dev = musb->controller; struct device *dev = musb->controller;
...@@ -405,29 +408,30 @@ dma_controller_create(struct musb *musb, void __iomem *pCoreBase) ...@@ -405,29 +408,30 @@ dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
return NULL; return NULL;
} }
controller = kzalloc(sizeof(struct musb_dma_controller), GFP_KERNEL); controller = kzalloc(sizeof(*controller), GFP_KERNEL);
if (!controller) if (!controller)
return NULL; return NULL;
controller->bChannelCount = MUSB_HSDMA_CHANNELS; controller->channel_count = MUSB_HSDMA_CHANNELS;
controller->pDmaPrivate = musb; controller->private_data = musb;
controller->pCoreBase = pCoreBase; controller->base = base;
controller->Controller.start = dma_controller_start; controller->controller.start = dma_controller_start;
controller->Controller.stop = dma_controller_stop; controller->controller.stop = dma_controller_stop;
controller->Controller.channel_alloc = dma_channel_allocate; controller->controller.channel_alloc = dma_channel_allocate;
controller->Controller.channel_release = dma_channel_release; controller->controller.channel_release = dma_channel_release;
controller->Controller.channel_program = dma_channel_program; controller->controller.channel_program = dma_channel_program;
controller->Controller.channel_abort = dma_channel_abort; controller->controller.channel_abort = dma_channel_abort;
if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
musb->controller->bus_id, &controller->Controller)) { musb->controller->bus_id, &controller->controller)) {
dev_err(dev, "request_irq %d failed!\n", irq); dev_err(dev, "request_irq %d failed!\n", irq);
dma_controller_destroy(&controller->Controller); dma_controller_destroy(&controller->controller);
return NULL; return NULL;
} }
controller->irq = irq; controller->irq = irq;
return &controller->Controller; return &controller->controller;
} }
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