提交 4426be36 编写于 作者: A Andy Shevchenko

pinctrl: intel: Switch to to embedded struct pingroup

Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
上级 98c23f60
...@@ -279,7 +279,7 @@ static const char *intel_get_group_name(struct pinctrl_dev *pctldev, ...@@ -279,7 +279,7 @@ static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
{ {
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->groups[group].name; return pctrl->soc->groups[group].grp.name;
} }
static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
...@@ -287,8 +287,8 @@ static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, ...@@ -287,8 +287,8 @@ static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
{ {
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->soc->groups[group].pins; *pins = pctrl->soc->groups[group].grp.pins;
*npins = pctrl->soc->groups[group].npins; *npins = pctrl->soc->groups[group].grp.npins;
return 0; return 0;
} }
...@@ -391,19 +391,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, ...@@ -391,19 +391,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
* All pins in the groups needs to be accessible and writable * All pins in the groups needs to be accessible and writable
* before we can enable the mux for this group. * before we can enable the mux for this group.
*/ */
for (i = 0; i < grp->npins; i++) { for (i = 0; i < grp->grp.npins; i++) {
if (!intel_pad_usable(pctrl, grp->pins[i])) { if (!intel_pad_usable(pctrl, grp->grp.pins[i])) {
raw_spin_unlock_irqrestore(&pctrl->lock, flags); raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return -EBUSY; return -EBUSY;
} }
} }
/* Now enable the mux setting for each pin in the group */ /* Now enable the mux setting for each pin in the group */
for (i = 0; i < grp->npins; i++) { for (i = 0; i < grp->grp.npins; i++) {
void __iomem *padcfg0; void __iomem *padcfg0;
u32 value; u32 value;
padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
value = readl(padcfg0); value = readl(padcfg0);
value &= ~PADCFG0_PMODE_MASK; value &= ~PADCFG0_PMODE_MASK;
......
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