提交 424749c7 编写于 作者: R Rajkumar Manoharan 提交者: John W. Linville

ath9k: perform ANI cycle in idle state

As of now the ANI cycle is executed only when the chip is awake.
On idle state case, the station wakes up from network sleep for
beacon reception. Since most of the time, ANI cycle is not syncing
with beacon wakeup, ANI cycle is ignored. Approx 5 mins once, the
calibration is performed. This could affect the connection stability
when the station is idle for long. Even though the OFDM and CCK phy
error rates are too high, ANI is unable to tune its immunity level
as quick enough due to rare execution.

Here the experiment shows that OFDM and CCK levels are at default
even on higher phy error rate.

listenTime=44 OFDM:3 errs=121977/s CCK:2 errs=440818/s ofdm_turn=1

This change ensures that ANI calibration will be exectued atleast
once for every 10 seconds. The below result shows improvements and
immunity levels are adopted quick enough.

listenTime=557 OFDM:4 errs=752/s CCK:4 errs=125/s ofdm_turn=0
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 b4764c80
...@@ -437,6 +437,7 @@ void ath9k_set_beacon(struct ath_softc *sc); ...@@ -437,6 +437,7 @@ void ath9k_set_beacon(struct ath_softc *sc);
#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
#define ATH_ANI_MAX_SKIP_COUNT 10
#define ATH_PAPRD_TIMEOUT 100 /* msecs */ #define ATH_PAPRD_TIMEOUT 100 /* msecs */
#define ATH_PLL_WORK_INTERVAL 100 #define ATH_PLL_WORK_INTERVAL 100
...@@ -642,6 +643,7 @@ enum sc_op_flags { ...@@ -642,6 +643,7 @@ enum sc_op_flags {
#define PS_WAIT_FOR_PSPOLL_DATA BIT(2) #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
#define PS_WAIT_FOR_TX_ACK BIT(3) #define PS_WAIT_FOR_TX_ACK BIT(3)
#define PS_BEACON_SYNC BIT(4) #define PS_BEACON_SYNC BIT(4)
#define PS_WAIT_FOR_ANI BIT(5)
struct ath_rate_table; struct ath_rate_table;
......
...@@ -834,6 +834,7 @@ struct ath_hw { ...@@ -834,6 +834,7 @@ struct ath_hw {
int coarse_low[5]; int coarse_low[5];
int firpwr[5]; int firpwr[5];
enum ath9k_ani_cmd ani_function; enum ath9k_ani_cmd ani_function;
u32 ani_skip_count;
#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
struct ath_btcoex_hw btcoex_hw; struct ath_btcoex_hw btcoex_hw;
......
...@@ -350,8 +350,18 @@ void ath_ani_calibrate(unsigned long data) ...@@ -350,8 +350,18 @@ void ath_ani_calibrate(unsigned long data)
ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
/* Only calibrate if awake */ /* Only calibrate if awake */
if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) {
if (++ah->ani_skip_count >= ATH_ANI_MAX_SKIP_COUNT) {
spin_lock_irqsave(&sc->sc_pm_lock, flags);
sc->ps_flags |= PS_WAIT_FOR_ANI;
spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
}
goto set_timer; goto set_timer;
}
ah->ani_skip_count = 0;
spin_lock_irqsave(&sc->sc_pm_lock, flags);
sc->ps_flags &= ~PS_WAIT_FOR_ANI;
spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
ath9k_ps_wakeup(sc); ath9k_ps_wakeup(sc);
......
...@@ -131,7 +131,8 @@ void ath9k_ps_restore(struct ath_softc *sc) ...@@ -131,7 +131,8 @@ void ath9k_ps_restore(struct ath_softc *sc)
!(sc->ps_flags & (PS_WAIT_FOR_BEACON | !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
PS_WAIT_FOR_CAB | PS_WAIT_FOR_CAB |
PS_WAIT_FOR_PSPOLL_DATA | PS_WAIT_FOR_PSPOLL_DATA |
PS_WAIT_FOR_TX_ACK))) { PS_WAIT_FOR_TX_ACK |
PS_WAIT_FOR_ANI))) {
mode = ATH9K_PM_NETWORK_SLEEP; mode = ATH9K_PM_NETWORK_SLEEP;
if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
ath9k_btcoex_stop_gen_timer(sc); ath9k_btcoex_stop_gen_timer(sc);
......
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