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Kernel
提交 41ebe9cd 编写于 作者: J John W. Linville
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Merge branch 'master' of git://git.infradead.org/users/linville/wireless-next into for-davem

上级 fd38f734 5c1381ac
展开全部 隐藏空白更改
内联 并排
Showing with 102247 addition and 2686 deletion
Documentation/networking/mac80211-injection.txt
浏览文件 @ 41ebe9cd
......@@ -23,6 +23,10 @@ radiotap headers and used to control injection:
IEEE80211_RADIOTAP_F_FRAG: frame will be fragmented if longer than the
current fragmentation threshold.
* IEEE80211_RADIOTAP_TX_FLAGS
IEEE80211_RADIOTAP_F_TX_NOACK: frame should be sent without waiting for
an ACK even if it is a unicast frame
The injection code can also skip all other currently defined radiotap fields
facilitating replay of captured radiotap headers directly.
......
drivers/net/wireless/Kconfig
浏览文件 @ 41ebe9cd
......@@ -271,6 +271,7 @@ config MWL8K
source "drivers/net/wireless/ath/Kconfig"
source "drivers/net/wireless/b43/Kconfig"
source "drivers/net/wireless/b43legacy/Kconfig"
source "drivers/net/wireless/brcm80211/Kconfig"
source "drivers/net/wireless/hostap/Kconfig"
source "drivers/net/wireless/ipw2x00/Kconfig"
source "drivers/net/wireless/iwlwifi/Kconfig"
......
drivers/net/wireless/Makefile
浏览文件 @ 41ebe9cd
......@@ -58,3 +58,6 @@ obj-$(CONFIG_WL12XX_PLATFORM_DATA) += wl12xx/
obj-$(CONFIG_IWM) += iwmc3200wifi/
obj-$(CONFIG_MWIFIEX) += mwifiex/
obj-$(CONFIG_BRCMFMAC) += brcm80211/
obj-$(CONFIG_BRCMUMAC) += brcm80211/
obj-$(CONFIG_BRCMSMAC) += brcm80211/
drivers/net/wireless/ath/ath.h
浏览文件 @ 41ebe9cd
......@@ -71,9 +71,7 @@ struct ath_regulatory {
char alpha2[2];
u16 country_code;
u16 max_power_level;
u32 tp_scale;
u16 current_rd;
u16 current_rd_ext;
int16_t power_limit;
struct reg_dmn_pair_mapping *regpair;
};
......
drivers/net/wireless/ath/ath5k/base.c
浏览文件 @ 41ebe9cd
......@@ -921,12 +921,6 @@ ath5k_txq_setup(struct ath5k_hw *ah,
*/
return ERR_PTR(qnum);
}
if (qnum >= ARRAY_SIZE(ah->txqs)) {
ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
qnum, ARRAY_SIZE(ah->txqs));
ath5k_hw_release_tx_queue(ah, qnum);
return ERR_PTR(-EINVAL);
}
txq = &ah->txqs[qnum];
if (!txq->setup) {
txq->qnum = qnum;
......
drivers/net/wireless/ath/ath9k/Makefile
浏览文件 @ 41ebe9cd
......@@ -21,6 +21,7 @@ ath9k_hw-y:= \
ar5008_phy.o \
ar9002_calib.o \
ar9003_calib.o \
ar9003_rtt.o \
calib.o \
eeprom.o \
eeprom_def.o \
......
drivers/net/wireless/ath/ath9k/ani.c
浏览文件 @ 41ebe9cd
......@@ -504,9 +504,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
ATH9K_ANI_CCK_WEAK_SIG_THR);
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
ATH9K_RX_FILTER_PHYERR);
ath9k_ani_restart(ah);
return;
}
......@@ -527,8 +524,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel);
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
~ATH9K_RX_FILTER_PHYERR);
ath9k_ani_restart(ah);
ENABLE_REGWRITE_BUFFER(ah);
......
drivers/net/wireless/ath/ath9k/ar5008_phy.c
浏览文件 @ 41ebe9cd
......@@ -763,10 +763,8 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
static int ar5008_hw_process_ini(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath_common *common = ath9k_hw_common(ah);
int i, regWrites = 0;
struct ieee80211_channel *channel = chan->chan;
u32 modesIndex, freqIndex;
switch (chan->chanmode) {
......@@ -903,14 +901,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
ar5008_hw_set_channel_regs(ah, chan);
ar5008_hw_init_chain_masks(ah);
ath9k_olc_init(ah);
/* Set TX power */
ah->eep_ops->set_txpower(ah, chan,
ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2,
channel->max_power * 2,
min((u32) MAX_RATE_POWER,
(u32) regulatory->power_limit), false);
ath9k_hw_apply_txpower(ah, chan);
/* Write analog registers */
if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
......
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
浏览文件 @ 41ebe9cd
......@@ -24,11 +24,11 @@ static const u32 ar9300_2p2_radio_postamble[][5] = {
{0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
{0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
{0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
{0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
{0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
{0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
{0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
{0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
{0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
{0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
{0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
{0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
};
......@@ -190,7 +190,7 @@ static const u32 ar9300_2p2_radio_core[][2] = {
{0x00016288, 0x05a20408},
{0x0001628c, 0x00038c07},
{0x00016290, 0x00000004},
{0x00016294, 0x458aa14f},
{0x00016294, 0x458a214f},
{0x00016380, 0x00000000},
{0x00016384, 0x00000000},
{0x00016388, 0x00800700},
......@@ -835,107 +835,107 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
{0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
{0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
{0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
{0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
{0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
{0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
{0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
{0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
{0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
{0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
{0x0000a518, 0x21002220, 0x21002220, 0x16000402, 0x16000402},
{0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
{0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
{0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
{0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
{0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
{0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
{0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
{0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
{0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
{0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
{0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861},
{0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81},
{0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83},
{0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84},
{0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3},
{0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5},
{0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9},
{0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb},
{0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
{0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
{0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
{0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
{0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
{0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
{0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
{0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
{0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
{0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
{0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
{0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
{0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
{0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
{0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
{0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
{0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
{0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
{0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
{0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
{0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
{0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
{0x0000a54c, 0x5a08442e, 0x5a08442e, 0x47001a83, 0x47001a83},
{0x0000a550, 0x5e0a4431, 0x5e0a4431, 0x4a001c84, 0x4a001c84},
{0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
{0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
{0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
{0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
{0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
{0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
{0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
{0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
{0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
{0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
{0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
{0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
{0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
{0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
{0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
{0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
{0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
{0x0000a598, 0x21802220, 0x21802220, 0x16800402, 0x16800402},
{0x0000a59c, 0x27802223, 0x27802223, 0x19800404, 0x19800404},
{0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
{0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
{0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
{0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
{0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
{0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
{0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
{0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
{0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
{0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861},
{0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81},
{0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83},
{0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84},
{0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3},
{0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5},
{0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9},
{0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb},
{0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
{0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
{0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
{0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
{0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
{0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
{0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
{0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
{0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
{0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
{0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
{0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
{0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
{0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
{0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
{0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
{0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
{0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
{0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
{0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
{0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
{0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
{0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
{0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
{0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
{0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
{0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
{0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
{0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
{0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
{0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
{0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
{0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
{0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
{0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
{0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
{0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
{0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
{0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
{0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
{0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
{0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
{0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
{0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
{0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
{0x0000b2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
{0x0000b2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
{0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
{0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
{0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
{0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
{0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
{0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
{0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
{0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
{0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
{0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
{0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
{0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
{0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
{0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
{0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
{0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
{0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
{0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
{0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
{0x0000c2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
{0x0000c2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
{0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
{0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
{0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
{0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
{0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
{0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
{0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
{0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
{0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
{0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
{0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
{0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
{0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
{0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
{0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
{0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
{0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
};
......
drivers/net/wireless/ath/ath9k/ar9003_calib.c
浏览文件 @ 41ebe9cd
......@@ -17,8 +17,9 @@
#include "hw.h"
#include "hw-ops.h"
#include "ar9003_phy.h"
#include "ar9003_rtt.h"
#define MAX_MEASUREMENT 8
#define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
#define MAX_MAG_DELTA 11
#define MAX_PHS_DELTA 10
......@@ -659,10 +660,12 @@ static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
u8 num_chains,
struct coeff *coeff)
struct coeff *coeff,
bool is_reusable)
{
int i, im, nmeasurement;
u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
struct ath9k_hw_cal_data *caldata = ah->caldata;
memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
......@@ -712,7 +715,13 @@ static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
coeff->iqc_coeff[0]);
if (caldata)
caldata->tx_corr_coeff[im][i] =
coeff->iqc_coeff[0];
}
if (caldata)
caldata->num_measures[i] = nmeasurement;
}
REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
......@@ -720,8 +729,10 @@ static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
return;
if (caldata)
caldata->done_txiqcal_once = is_reusable;
return;
}
static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
......@@ -748,7 +759,7 @@ static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
return true;
}
static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable)
{
struct ath_common *common = ath9k_hw_common(ah);
const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
......@@ -837,7 +848,8 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
coeff.phs_coeff[i][im] -= 128;
}
}
ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains,
&coeff, is_reusable);
return;
......@@ -845,11 +857,129 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
return;
}
static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
{
struct ath9k_hw_cal_data *caldata = ah->caldata;
u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
int i, im;
memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
if (!AR_SREV_9485(ah)) {
tx_corr_coeff[i * 2][1] =
tx_corr_coeff[(i * 2) + 1][1] =
AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
tx_corr_coeff[i * 2][2] =
tx_corr_coeff[(i * 2) + 1][2] =
AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
}
}
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
if (!(ah->txchainmask & (1 << i)))
continue;
for (im = 0; im < caldata->num_measures[i]; im++) {
if ((im % 2) == 0)
REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
caldata->tx_corr_coeff[im][i]);
else
REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
caldata->tx_corr_coeff[im][i]);
}
}
REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
}
static bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
{
struct ath9k_rtt_hist *hist;
u32 *table;
int i;
bool restore;
if (!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT) || !ah->caldata)
return false;
hist = &ah->caldata->rtt_hist;
ar9003_hw_rtt_enable(ah);
ar9003_hw_rtt_set_mask(ah, 0x10);
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
if (!(ah->rxchainmask & (1 << i)))
continue;
table = &hist->table[i][hist->num_readings][0];
ar9003_hw_rtt_load_hist(ah, i, table);
}
restore = ar9003_hw_rtt_force_restore(ah);
ar9003_hw_rtt_disable(ah);
return restore;
}
static bool ar9003_hw_init_cal(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct ath_common *common = ath9k_hw_common(ah);
bool txiqcal_done = false;
struct ath9k_hw_cal_data *caldata = ah->caldata;
bool txiqcal_done = false, txclcal_done = false;
bool is_reusable = true, status = true;
bool run_rtt_cal = false, run_agc_cal;
bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
AR_PHY_AGC_CONTROL_FLTR_CAL |
AR_PHY_AGC_CONTROL_PKDET_CAL;
int i, j;
u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
AR_PHY_CL_TAB_1,
AR_PHY_CL_TAB_2 };
if (rtt) {
if (!ar9003_hw_rtt_restore(ah, chan))
run_rtt_cal = true;
ath_dbg(common, ATH_DBG_CALIBRATE, "RTT restore %s\n",
run_rtt_cal ? "failed" : "succeed");
}
run_agc_cal = run_rtt_cal;
if (run_rtt_cal) {
ar9003_hw_rtt_enable(ah);
ar9003_hw_rtt_set_mask(ah, 0x00);
ar9003_hw_rtt_clear_hist(ah);
}
if (rtt && !run_rtt_cal) {
agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
agc_supp_cals &= agc_ctrl;
agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
AR_PHY_AGC_CONTROL_FLTR_CAL |
AR_PHY_AGC_CONTROL_PKDET_CAL);
REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
}
if (ah->enabled_cals & TX_CL_CAL) {
if (caldata && caldata->done_txclcal_once)
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
AR_PHY_CL_CAL_ENABLE);
else {
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
AR_PHY_CL_CAL_ENABLE);
run_agc_cal = true;
}
}
if (!(ah->enabled_cals & TX_IQ_CAL))
goto skip_tx_iqcal;
/* Do Tx IQ Calibration */
REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
......@@ -860,30 +990,96 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
* For AR9485 or later chips, TxIQ cal runs as part of
* AGC calibration
*/
if (AR_SREV_9485_OR_LATER(ah))
txiqcal_done = true;
else {
txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
udelay(5);
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
}
/* Calibrate the AGC */
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
REG_READ(ah, AR_PHY_AGC_CONTROL) |
AR_PHY_AGC_CONTROL_CAL);
/* Poll for offset calibration complete */
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
0, AH_WAIT_TIMEOUT)) {
if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
if (caldata && !caldata->done_txiqcal_once)
REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
else
REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
txiqcal_done = run_agc_cal = true;
goto skip_tx_iqcal;
} else if (caldata && !caldata->done_txiqcal_once)
run_agc_cal = true;
txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
udelay(5);
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
skip_tx_iqcal:
if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
/* Calibrate the AGC */
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
REG_READ(ah, AR_PHY_AGC_CONTROL) |
AR_PHY_AGC_CONTROL_CAL);
/* Poll for offset calibration complete */
status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_CAL,
0, AH_WAIT_TIMEOUT);
}
if (rtt && !run_rtt_cal) {
agc_ctrl |= agc_supp_cals;
REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
}
if (!status) {
if (run_rtt_cal)
ar9003_hw_rtt_disable(ah);
ath_dbg(common, ATH_DBG_CALIBRATE,
"offset calibration failed to complete in 1ms; noisy environment?\n");
"offset calibration failed to complete in 1ms;"
"noisy environment?\n");
return false;
}
if (txiqcal_done)
ar9003_hw_tx_iq_cal_post_proc(ah);
ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
else if (caldata && caldata->done_txiqcal_once)
ar9003_hw_tx_iq_cal_reload(ah);
#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
if (caldata && (ah->enabled_cals & TX_CL_CAL)) {
txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
AR_PHY_AGC_CONTROL_CLC_SUCCESS);
if (caldata->done_txclcal_once) {
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
if (!(ah->txchainmask & (1 << i)))
continue;
for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
caldata->tx_clcal[i][j]);
}
} else if (is_reusable && txclcal_done) {
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
if (!(ah->txchainmask & (1 << i)))
continue;
for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
caldata->tx_clcal[i][j] =
REG_READ(ah,
CL_TAB_ENTRY(cl_idx[i]));
}
caldata->done_txclcal_once = true;
}
}
#undef CL_TAB_ENTRY
if (run_rtt_cal && caldata) {
struct ath9k_rtt_hist *hist = &caldata->rtt_hist;
if (is_reusable && (hist->num_readings < RTT_HIST_MAX)) {
u32 *table;
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
if (!(ah->rxchainmask & (1 << i)))
continue;
table = &hist->table[i][hist->num_readings][0];
ar9003_hw_rtt_fill_hist(ah, i, table);
}
}
ar9003_hw_rtt_disable(ah);
}
ath9k_hw_loadnf(ah, chan);
ath9k_hw_start_nfcal(ah, true);
......@@ -912,8 +1108,8 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
if (ah->cal_list_curr)
ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
if (ah->caldata)
ah->caldata->CalValid = 0;
if (caldata)
caldata->CalValid = 0;
return true;
}
......
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
浏览文件 @ 41ebe9cd
......@@ -2995,8 +2995,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
return get_unaligned_be16(eep->macAddr + 4);
case EEP_REG_0:
return le16_to_cpu(pBase->regDmn[0]);
case EEP_REG_1:
return le16_to_cpu(pBase->regDmn[1]);
case EEP_OP_CAP:
return pBase->deviceCap;
case EEP_OP_MODE:
......@@ -3021,6 +3019,10 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
return (pBase->miscConfiguration >> 0x3) & 0x1;
case EEP_ANT_DIV_CTL1:
return eep->base_ext1.ant_div_control;
case EEP_ANTENNA_GAIN_5G:
return eep->modalHeader5G.antennaGain;
case EEP_ANTENNA_GAIN_2G:
return eep->modalHeader2G.antennaGain;
default:
return 0;
}
......@@ -3554,7 +3556,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
else if (AR_SREV_9480(ah))
else if (AR_SREV_9462(ah))
REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
else {
REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
......@@ -3633,20 +3635,20 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
if (AR_SREV_9480(ah)) {
if (AR_SREV_9480_10(ah)) {
if (AR_SREV_9462(ah)) {
if (AR_SREV_9462_10(ah)) {
value &= ~AR_SWITCH_TABLE_COM_SPDT;
value |= 0x00100000;
}
REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
AR_SWITCH_TABLE_COM_AR9480_ALL, value);
AR_SWITCH_TABLE_COM_AR9462_ALL, value);
} else
REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
AR_SWITCH_TABLE_COM_ALL, value);
/*
* AR9480 defines new switch table for BT/WLAN,
* AR9462 defines new switch table for BT/WLAN,
* here's new field name in XXX.ref for both 2G and 5G.
* Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
* 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
......@@ -3658,7 +3660,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
* 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
* SWITCH_TABLE_COM_SPDT_WLAN_IDLE
*/
if (AR_SREV_9480_20_OR_LATER(ah)) {
if (AR_SREV_9462_20_OR_LATER(ah)) {
value = ar9003_switch_com_spdt_get(ah, is2ghz);
REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
AR_SWITCH_TABLE_COM_SPDT_ALL, value);
......@@ -3907,7 +3909,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
return;
} else if (AR_SREV_9480(ah)) {
} else if (AR_SREV_9462(ah)) {
reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
REG_WRITE(ah, AR_PHY_PMU1, reg_val);
} else {
......@@ -3938,7 +3940,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
AR_PHY_PMU2_PGM))
udelay(10);
} else if (AR_SREV_9480(ah))
} else if (AR_SREV_9462(ah))
REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
else {
reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
......@@ -4525,7 +4527,7 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
if (AR_SREV_9480_20(ah))
if (AR_SREV_9462_20(ah))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
......@@ -4764,20 +4766,14 @@ static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
struct ath9k_channel *chan,
u8 *pPwrArray, u16 cfgCtl,
u8 twiceAntennaReduction,
u8 twiceMaxRegulatoryPower,
u8 antenna_reduction,
u16 powerLimit)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath_common *common = ath9k_hw_common(ah);
struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
u16 twiceMaxEdgePower = MAX_RATE_POWER;
static const u16 tpScaleReductionTable[5] = {
0, 3, 6, 9, MAX_RATE_POWER
};
int i;
int16_t twiceLargestAntenna;
u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
u16 scaledPower = 0, minCtlPower;
static const u16 ctlModesFor11a[] = {
CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
};
......@@ -4795,28 +4791,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
bool is2ghz = IS_CHAN_2GHZ(chan);
ath9k_hw_get_channel_centers(ah, chan, &centers);
/* Compute TxPower reduction due to Antenna Gain */
if (is2ghz)
twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
else
twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
twiceLargestAntenna, 0);
/*
* scaledPower is the minimum of the user input power level
* and the regulatory allowed power level
*/
maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
maxRegAllowedPower -=
(tpScaleReductionTable[(regulatory->tp_scale)] * 2);
}
scaledPower = min(powerLimit, maxRegAllowedPower);
scaledPower = powerLimit - antenna_reduction;
/*
* Reduce scaled Power by number of chains active to get
......@@ -5003,7 +4978,6 @@ static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
struct ath9k_channel *chan, u16 cfgCtl,
u8 twiceAntennaReduction,
u8 twiceMaxRegulatoryPower,
u8 powerLimit, bool test)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
......@@ -5056,7 +5030,6 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
ar9003_hw_set_power_per_rate_table(ah, chan,
targetPowerValT2, cfgCtl,
twiceAntennaReduction,
twiceMaxRegulatoryPower,
powerLimit);
if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
......
drivers/net/wireless/ath/ath9k/ar9003_hw.c
浏览文件 @ 41ebe9cd
......@@ -22,8 +22,8 @@
#include "ar9330_1p1_initvals.h"
#include "ar9330_1p2_initvals.h"
#include "ar9580_1p0_initvals.h"
#include "ar9480_1p0_initvals.h"
#include "ar9480_2p0_initvals.h"
#include "ar9462_1p0_initvals.h"
#include "ar9462_2p0_initvals.h"
/* General hardware code for the AR9003 hadware family */
......@@ -35,13 +35,13 @@
static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
{
#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
ar9480_pciephy_pll_on_clkreq_disable_L1_2p0
ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
#define AR9480_BB_CTX_COEFJ(x) \
ar9480_##x##_baseband_core_txfir_coeff_japan_2484
#define AR9462_BB_CTX_COEFJ(x) \
ar9462_##x##_baseband_core_txfir_coeff_japan_2484
#define AR9480_BBC_TXIFR_COEFFJ \
ar9480_2p0_baseband_core_txfir_coeff_japan_2484
#define AR9462_BBC_TXIFR_COEFFJ \
ar9462_2p0_baseband_core_txfir_coeff_japan_2484
if (AR_SREV_9330_11(ah)) {
/* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
......@@ -264,107 +264,107 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9485_1_1_pcie_phy_clkreq_disable_L1,
ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
2);
} else if (AR_SREV_9480_10(ah)) {
} else if (AR_SREV_9462_10(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_1p0_mac_core,
ARRAY_SIZE(ar9480_1p0_mac_core), 2);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core,
ARRAY_SIZE(ar9462_1p0_mac_core), 2);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
ar9480_1p0_mac_postamble,
ARRAY_SIZE(ar9480_1p0_mac_postamble),
ar9462_1p0_mac_postamble,
ARRAY_SIZE(ar9462_1p0_mac_postamble),
5);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
ar9480_1p0_baseband_core,
ARRAY_SIZE(ar9480_1p0_baseband_core),
ar9462_1p0_baseband_core,
ARRAY_SIZE(ar9462_1p0_baseband_core),
2);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
ar9480_1p0_baseband_postamble,
ARRAY_SIZE(ar9480_1p0_baseband_postamble), 5);
ar9462_1p0_baseband_postamble,
ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
ar9480_1p0_radio_core,
ARRAY_SIZE(ar9480_1p0_radio_core), 2);
ar9462_1p0_radio_core,
ARRAY_SIZE(ar9462_1p0_radio_core), 2);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
ar9480_1p0_radio_postamble,
ARRAY_SIZE(ar9480_1p0_radio_postamble), 5);
ar9462_1p0_radio_postamble,
ARRAY_SIZE(ar9462_1p0_radio_postamble), 5);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
ar9480_1p0_soc_preamble,
ARRAY_SIZE(ar9480_1p0_soc_preamble), 2);
ar9462_1p0_soc_preamble,
ARRAY_SIZE(ar9462_1p0_soc_preamble), 2);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
ar9480_1p0_soc_postamble,
ARRAY_SIZE(ar9480_1p0_soc_postamble), 5);
ar9462_1p0_soc_postamble,
ARRAY_SIZE(ar9462_1p0_soc_postamble), 5);
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_rx_gain_table_1p0,
ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), 2);
ar9462_common_rx_gain_table_1p0,
ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2);
/* Awake -> Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9480_pcie_phy_clkreq_disable_L1_1p0,
ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0),
ar9462_pcie_phy_clkreq_disable_L1_1p0,
ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
2);
/* Sleep -> Awake Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9480_pcie_phy_clkreq_disable_L1_1p0,
ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0),
ar9462_pcie_phy_clkreq_disable_L1_1p0,
ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
2);
INIT_INI_ARRAY(&ah->iniModesAdditional,
ar9480_modes_fast_clock_1p0,
ARRAY_SIZE(ar9480_modes_fast_clock_1p0), 3);
ar9462_modes_fast_clock_1p0,
ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
AR9480_BB_CTX_COEFJ(1p0),
ARRAY_SIZE(AR9480_BB_CTX_COEFJ(1p0)), 2);
AR9462_BB_CTX_COEFJ(1p0),
ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2);
} else if (AR_SREV_9480_20(ah)) {
} else if (AR_SREV_9462_20(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_2p0_mac_core,
ARRAY_SIZE(ar9480_2p0_mac_core), 2);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
ARRAY_SIZE(ar9462_2p0_mac_core), 2);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
ar9480_2p0_mac_postamble,
ARRAY_SIZE(ar9480_2p0_mac_postamble), 5);
ar9462_2p0_mac_postamble,
ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
ar9480_2p0_baseband_core,
ARRAY_SIZE(ar9480_2p0_baseband_core), 2);
ar9462_2p0_baseband_core,
ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
ar9480_2p0_baseband_postamble,
ARRAY_SIZE(ar9480_2p0_baseband_postamble), 5);
ar9462_2p0_baseband_postamble,
ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
ar9480_2p0_radio_core,
ARRAY_SIZE(ar9480_2p0_radio_core), 2);
ar9462_2p0_radio_core,
ARRAY_SIZE(ar9462_2p0_radio_core), 2);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
ar9480_2p0_radio_postamble,
ARRAY_SIZE(ar9480_2p0_radio_postamble), 5);
ar9462_2p0_radio_postamble,
ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
ar9480_2p0_radio_postamble_sys2ant,
ARRAY_SIZE(ar9480_2p0_radio_postamble_sys2ant),
ar9462_2p0_radio_postamble_sys2ant,
ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
5);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
ar9480_2p0_soc_preamble,
ARRAY_SIZE(ar9480_2p0_soc_preamble), 2);
ar9462_2p0_soc_preamble,
ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
ar9480_2p0_soc_postamble,
ARRAY_SIZE(ar9480_2p0_soc_postamble), 5);
ar9462_2p0_soc_postamble,
ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_rx_gain_table_2p0,
ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), 2);
ar9462_common_rx_gain_table_2p0,
ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
ar9480_2p0_BTCOEX_MAX_TXPWR_table,
ARRAY_SIZE(ar9480_2p0_BTCOEX_MAX_TXPWR_table),
ar9462_2p0_BTCOEX_MAX_TXPWR_table,
ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
2);
/* Awake -> Sleep Setting */
......@@ -380,15 +380,15 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
/* Fast clock modal settings */
INIT_INI_ARRAY(&ah->iniModesAdditional,
ar9480_modes_fast_clock_2p0,
ARRAY_SIZE(ar9480_modes_fast_clock_2p0), 3);
ar9462_modes_fast_clock_2p0,
ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
AR9480_BB_CTX_COEFJ(2p0),
ARRAY_SIZE(AR9480_BB_CTX_COEFJ(2p0)), 2);
AR9462_BB_CTX_COEFJ(2p0),
ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
INIT_INI_ARRAY(&ah->ini_japan2484, AR9480_BBC_TXIFR_COEFFJ,
ARRAY_SIZE(AR9480_BBC_TXIFR_COEFFJ), 2);
INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
} else if (AR_SREV_9580(ah)) {
/* mac */
......@@ -537,15 +537,15 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
ar9580_1p0_lowest_ob_db_tx_gain_table,
ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
5);
else if (AR_SREV_9480_10(ah))
else if (AR_SREV_9462_10(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9480_modes_low_ob_db_tx_gain_table_1p0,
ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_1p0),
ar9462_modes_low_ob_db_tx_gain_table_1p0,
ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0),
5);
else if (AR_SREV_9480_20(ah))
else if (AR_SREV_9462_20(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9480_modes_low_ob_db_tx_gain_table_2p0,
ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_2p0),
ar9462_modes_low_ob_db_tx_gain_table_2p0,
ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
5);
else
INIT_INI_ARRAY(&ah->iniModesTxGain,
......@@ -581,15 +581,15 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
ar9580_1p0_high_ob_db_tx_gain_table,
ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
5);
else if (AR_SREV_9480_10(ah))
else if (AR_SREV_9462_10(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9480_modes_high_ob_db_tx_gain_table_1p0,
ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_1p0),
ar9462_modes_high_ob_db_tx_gain_table_1p0,
ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0),
5);
else if (AR_SREV_9480_20(ah))
else if (AR_SREV_9462_20(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9480_modes_high_ob_db_tx_gain_table_2p0,
ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_2p0),
ar9462_modes_high_ob_db_tx_gain_table_2p0,
ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
5);
else
INIT_INI_ARRAY(&ah->iniModesTxGain,
......@@ -712,15 +712,15 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
ar9580_1p0_rx_gain_table,
ARRAY_SIZE(ar9580_1p0_rx_gain_table),
2);
else if (AR_SREV_9480_10(ah))
else if (AR_SREV_9462_10(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_rx_gain_table_1p0,
ARRAY_SIZE(ar9480_common_rx_gain_table_1p0),
ar9462_common_rx_gain_table_1p0,
ARRAY_SIZE(ar9462_common_rx_gain_table_1p0),
2);
else if (AR_SREV_9480_20(ah))
else if (AR_SREV_9462_20(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_rx_gain_table_2p0,
ARRAY_SIZE(ar9480_common_rx_gain_table_2p0),
ar9462_common_rx_gain_table_2p0,
ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
2);
else
INIT_INI_ARRAY(&ah->iniModesRxGain,
......@@ -751,15 +751,15 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
ar9485Common_wo_xlna_rx_gain_1_1,
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
2);
else if (AR_SREV_9480_10(ah))
else if (AR_SREV_9462_10(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_wo_xlna_rx_gain_table_1p0,
ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_1p0),
ar9462_common_wo_xlna_rx_gain_table_1p0,
ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0),
2);
else if (AR_SREV_9480_20(ah))
else if (AR_SREV_9462_20(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_wo_xlna_rx_gain_table_2p0,
ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_2p0),
ar9462_common_wo_xlna_rx_gain_table_2p0,
ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
2);
else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
......@@ -775,14 +775,14 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
{
if (AR_SREV_9480_10(ah))
if (AR_SREV_9462_10(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_mixed_rx_gain_table_1p0,
ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_1p0), 2);
else if (AR_SREV_9480_20(ah))
ar9462_common_mixed_rx_gain_table_1p0,
ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2);
else if (AR_SREV_9462_20(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9480_common_mixed_rx_gain_table_2p0,
ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_2p0), 2);
ar9462_common_mixed_rx_gain_table_2p0,
ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
}
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
......
drivers/net/wireless/ath/ath9k/ar9003_mac.c
浏览文件 @ 41ebe9cd
......@@ -525,8 +525,8 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
rxs->rs_status |= ATH9K_RXERR_DECRYPT;
else if (rxsp->status11 & AR_MichaelErr)
rxs->rs_status |= ATH9K_RXERR_MIC;
else if (rxsp->status11 & AR_KeyMiss)
rxs->rs_status |= ATH9K_RXERR_DECRYPT;
if (rxsp->status11 & AR_KeyMiss)
rxs->rs_status |= ATH9K_RXERR_KEYMISS;
}
return 0;
......
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
浏览文件 @ 41ebe9cd
......@@ -19,7 +19,6 @@
void ar9003_paprd_enable(struct ath_hw *ah, bool val)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath9k_channel *chan = ah->curchan;
struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
......@@ -54,13 +53,7 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
if (val) {
ah->paprd_table_write_done = true;
ah->eep_ops->set_txpower(ah, chan,
ath9k_regd_get_ctl(regulatory, chan),
chan->chan->max_antenna_gain * 2,
chan->chan->max_power * 2,
min((u32) MAX_RATE_POWER,
(u32) regulatory->power_limit), false);
ath9k_hw_apply_txpower(ah, chan);
}
REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
......@@ -207,7 +200,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1);
val = AR_SREV_9480(ah) ? 0x91 : 147;
val = AR_SREV_9462(ah) ? 0x91 : 147;
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
......@@ -218,7 +211,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
if (AR_SREV_9485(ah) || AR_SREV_9480(ah))
if (AR_SREV_9485(ah) || AR_SREV_9462(ah))
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
-3);
......@@ -226,7 +219,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
-6);
val = AR_SREV_9480(ah) ? -10 : -15;
val = AR_SREV_9462(ah) ? -10 : -15;
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
val);
......
drivers/net/wireless/ath/ath9k/ar9003_phy.c
浏览文件 @ 41ebe9cd
......@@ -559,7 +559,7 @@ static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
else if (AR_SREV_9480(ah))
else if (AR_SREV_9462(ah))
/* xxx only when MCI support is enabled */
REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
else
......@@ -631,9 +631,7 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
static int ar9003_hw_process_ini(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
unsigned int regWrites = 0, i;
struct ieee80211_channel *channel = chan->chan;
u32 modesIndex;
switch (chan->chanmode) {
......@@ -664,7 +662,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
if (i == ATH_INI_POST && AR_SREV_9480_20(ah))
if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
ar9003_hw_prog_ini(ah,
&ah->ini_radio_post_sys2ant,
modesIndex);
......@@ -687,20 +685,27 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
if (AR_SREV_9480(ah))
if (AR_SREV_9462(ah))
ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
ah->modes_index = modesIndex;
ar9003_hw_override_ini(ah);
ar9003_hw_set_channel_regs(ah, chan);
ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
ath9k_hw_apply_txpower(ah, chan);
/* Set TX power */
ah->eep_ops->set_txpower(ah, chan,
ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2,
channel->max_power * 2,
min((u32) MAX_RATE_POWER,
(u32) regulatory->power_limit), false);
if (AR_SREV_9462(ah)) {
if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
ah->enabled_cals |= TX_IQ_CAL;
else
ah->enabled_cals &= ~TX_IQ_CAL;
if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
ah->enabled_cals |= TX_CL_CAL;
else
ah->enabled_cals &= ~TX_CL_CAL;
}
return 0;
}
......@@ -1256,6 +1261,73 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
}
static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
struct ath9k_channel *chan,
u8 *ini_reloaded)
{
unsigned int regWrites = 0;
u32 modesIndex;
switch (chan->chanmode) {
case CHANNEL_A:
case CHANNEL_A_HT20:
modesIndex = 1;
break;
case CHANNEL_A_HT40PLUS:
case CHANNEL_A_HT40MINUS:
modesIndex = 2;
break;
case CHANNEL_G:
case CHANNEL_G_HT20:
case CHANNEL_B:
modesIndex = 4;
break;
case CHANNEL_G_HT40PLUS:
case CHANNEL_G_HT40MINUS:
modesIndex = 3;
break;
default:
return -EINVAL;
}
if (modesIndex == ah->modes_index) {
*ini_reloaded = false;
goto set_rfmode;
}
ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
if (AR_SREV_9462_20(ah))
ar9003_hw_prog_ini(ah,
&ah->ini_radio_post_sys2ant,
modesIndex);
REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
/*
* For 5GHz channels requiring Fast Clock, apply
* different modal values.
*/
if (IS_CHAN_A_FAST_CLOCK(ah, chan))
REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites);
if (AR_SREV_9330(ah))
REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
ah->modes_index = modesIndex;
*ini_reloaded = true;
set_rfmode:
ar9003_hw_set_rfmode(ah, chan);
return 0;
}
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
{
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
......@@ -1284,6 +1356,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
priv_ops->do_getnf = ar9003_hw_do_getnf;
priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
priv_ops->set_radar_params = ar9003_hw_set_radar_params;
priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
......
drivers/net/wireless/ath/ath9k/ar9003_phy.h
浏览文件 @ 41ebe9cd
......@@ -325,10 +325,10 @@
#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
#define AR_PHY_CCA_NOM_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -110)
#define AR_PHY_CCA_NOM_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -115)
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -125)
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -125)
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
......@@ -572,6 +572,8 @@
#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
#define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
0x3c4 : 0x444)
#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \
0x3c8 : 0x448)
#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \
......@@ -582,8 +584,6 @@
(AR_SREV_9485(ah) ? \
0x3d0 : 0x450) + ((_i) << 2))
#define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)
#define AR_PHY_RTT_TABLE_SW_INTF_B (AR_SM_BASE + 0x384)
#define AR_PHY_RTT_TABLE_SW_INTF_1_B0 (AR_SM_BASE + 0x388)
#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
......@@ -608,9 +608,9 @@
#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \
#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
0x4c0 : 0x4c4))
#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \
#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
0x4c4 : 0x4c8))
#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
......@@ -625,7 +625,7 @@
#define AR_PHY_65NM_CH0_RXTX4 0x1610c
#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
((AR_SREV_9480(ah) ? 0x1628c : 0x16280)))
((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
#define AR_CH0_TOP_XPABIASLVL (0x300)
#define AR_CH0_TOP_XPABIASLVL_S (8)
......@@ -638,8 +638,8 @@
#define AR_SWITCH_TABLE_COM_ALL (0xffff)
#define AR_SWITCH_TABLE_COM_ALL_S (0)
#define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff)
#define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0)
#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
......@@ -679,11 +679,11 @@
#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
#define AR_CH0_XTAL_CAPOUTDAC_S 17
#define AR_PHY_PMU1 (AR_SREV_9480(ah) ? 0x16340 : 0x16c40)
#define AR_PHY_PMU1 (AR_SREV_9462(ah) ? 0x16340 : 0x16c40)
#define AR_PHY_PMU1_PWD 0x1
#define AR_PHY_PMU1_PWD_S 0
#define AR_PHY_PMU2 (AR_SREV_9480(ah) ? 0x16344 : 0x16c44)
#define AR_PHY_PMU2 (AR_SREV_9462(ah) ? 0x16344 : 0x16c44)
#define AR_PHY_PMU2_PGM 0x00200000
#define AR_PHY_PMU2_PGM_S 21
......@@ -823,6 +823,22 @@
#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001
#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0
#define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E
#define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1
#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080
#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7
#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS 0x00000001
#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S 0
#define AR_PHY_RTT_SW_RTT_TABLE_WRITE 0x00000002
#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S 1
#define AR_PHY_RTT_SW_RTT_TABLE_ADDR 0x0000001C
#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S 2
#define AR_PHY_RTT_SW_RTT_TABLE_DATA 0xFFFFFFF0
#define AR_PHY_RTT_SW_RTT_TABLE_DATA_S 4
#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000
#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31
#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
......@@ -905,9 +921,9 @@
#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8)
#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \
#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
0x4c0 : 0x4c4))
#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \
#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
0x4c4 : 0x4c8))
#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
......@@ -915,6 +931,10 @@
#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + (i) ? \
AR_SM1_BASE : AR_SM_BASE)
#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + (i) ? \
AR_SM1_BASE : AR_SM_BASE)
/*
* Channel 2 Register Map
*/
......@@ -981,7 +1001,7 @@
#define AR_GLB_BASE 0x20000
#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \
(AR_SREV_9480_20(_ah) ? 0x4c : 0x50))
(AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
#define AR_GLB_STATUS (AR_GLB_BASE + 0x48)
/*
......
drivers/net/wireless/ath/ath9k/ar9003_rtt.c 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010-2011 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "hw.h"
#include "ar9003_phy.h"
#define RTT_RESTORE_TIMEOUT 1000
#define RTT_ACCESS_TIMEOUT 100
#define RTT_BAD_VALUE 0x0bad0bad
/*
* RTT (Radio Retention Table) hardware implementation information
*
* There is an internal table (i.e. the rtt) for each chain (or bank).
* Each table contains 6 entries and each entry is corresponding to
* a specific calibration parameter as depicted below.
* 0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
* 3 - Filter cal (filterfc)
* 4 - RX gain settings
* 5 - Peak detector offset calibration (agc_caldac)
*/
void ar9003_hw_rtt_enable(struct ath_hw *ah)
{
REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
}
void ar9003_hw_rtt_disable(struct ath_hw *ah)
{
REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
}
void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
{
REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
}
bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
{
if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
0, RTT_RESTORE_TIMEOUT))
return false;
REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);
if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
0, RTT_RESTORE_TIMEOUT))
return false;
return true;
}
static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
u32 index, u32 data28)
{
u32 val;
val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
udelay(1);
val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
udelay(1);
if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
RTT_ACCESS_TIMEOUT))
return;
val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
udelay(1);
ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
RTT_ACCESS_TIMEOUT);
}
void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table)
{
int i;
for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
ar9003_hw_rtt_load_hist_entry(ah, chain, i, table[i]);
}
static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
{
u32 val;
val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
udelay(1);
val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
udelay(1);
if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
RTT_ACCESS_TIMEOUT))
return RTT_BAD_VALUE;
val = REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain));
return val;
}
void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table)
{
int i;
for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
table[i] = ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
}
void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
{
int i, j;
for (i = 0; i < AR9300_MAX_CHAINS; i++) {
if (!(ah->rxchainmask & (1 << i)))
continue;
for (j = 0; j < MAX_RTT_TABLE_ENTRY; j++)
ar9003_hw_rtt_load_hist_entry(ah, i, j, 0);
}
}
drivers/net/wireless/ath/ath9k/ar9003_rtt.h 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010-2011 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef AR9003_RTT_H
#define AR9003_RTT_H
void ar9003_hw_rtt_enable(struct ath_hw *ah);
void ar9003_hw_rtt_disable(struct ath_hw *ah);
void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask);
bool ar9003_hw_rtt_force_restore(struct ath_hw *ah);
void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table);
void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table);
void ar9003_hw_rtt_clear_hist(struct ath_hw *ah);
#endif
drivers/net/wireless/ath/ath9k/ar9480_1p0_initvals.h → drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h
浏览文件 @ 41ebe9cd
......@@ -14,12 +14,12 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef INITVALS_9480_1P0_H
#define INITVALS_9480_1P0_H
#ifndef INITVALS_9462_1P0_H
#define INITVALS_9462_1P0_H
/* AR9480 1.0 */
/* AR9462 1.0 */
static const u32 ar9480_1p0_mac_core[][2] = {
static const u32 ar9462_1p0_mac_core[][2] = {
/* Addr allmodes */
{0x00000008, 0x00000000},
{0x00000030, 0x00060085},
......@@ -183,27 +183,27 @@ static const u32 ar9480_1p0_mac_core[][2] = {
{0x000083d0, 0x000301ff},
};
static const u32 ar9480_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
static const u32 ar9462_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
/* Addr allmodes */
{0x0000a398, 0x00000000},
{0x0000a39c, 0x6f7f0301},
{0x0000a3a0, 0xca9228ee},
};
static const u32 ar9480_1p0_sys3ant[][2] = {
static const u32 ar9462_1p0_sys3ant[][2] = {
/* Addr allmodes */
{0x00063280, 0x00040807},
{0x00063284, 0x104ccccc},
};
static const u32 ar9480_pcie_phy_clkreq_enable_L1_1p0[][2] = {
static const u32 ar9462_pcie_phy_clkreq_enable_L1_1p0[][2] = {
/* Addr allmodes */
{0x00018c00, 0x10053e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000580c},
};
static const u32 ar9480_1p0_mac_core_emulation[][2] = {
static const u32 ar9462_1p0_mac_core_emulation[][2] = {
/* Addr allmodes */
{0x00000030, 0x00060085},
{0x00000044, 0x00000008},
......@@ -211,7 +211,7 @@ static const u32 ar9480_1p0_mac_core_emulation[][2] = {
{0x00008344, 0xaa4a105b},
};
static const u32 ar9480_common_rx_gain_table_ar9280_2p0_1p0[][2] = {
static const u32 ar9462_common_rx_gain_table_ar9280_2p0_1p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x02000101},
{0x0000a004, 0x02000102},
......@@ -513,7 +513,7 @@ static const u32 ar9200_ar9280_2p0_radio_core_1p0[][2] = {
{0x00007894, 0x5a108000},
};
static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = {
static const u32 ar9462_1p0_baseband_postamble_emulation[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221},
......@@ -535,14 +535,14 @@ static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = {
{0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
};
static const u32 ar9480_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = {
static const u32 ar9462_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = {
/* Addr allmodes */
{0x00018c00, 0x10012e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000580c},
};
static const u32 ar9480_common_rx_gain_table_1p0[][2] = {
static const u32 ar9462_common_rx_gain_table_1p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
......@@ -802,7 +802,7 @@ static const u32 ar9480_common_rx_gain_table_1p0[][2] = {
{0x0000b1fc, 0x00000196},
};
static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = {
static const u32 ar9462_modes_high_ob_db_tx_gain_table_1p0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
{0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
......@@ -867,7 +867,7 @@ static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = {
{0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
};
static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = {
static const u32 ar9462_common_wo_xlna_rx_gain_table_1p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
......@@ -1127,7 +1127,7 @@ static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = {
{0x0000b1fc, 0x00000196},
};
static const u32 ar9480_1p0_mac_postamble[][5] = {
static const u32 ar9462_1p0_mac_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
......@@ -1139,13 +1139,13 @@ static const u32 ar9480_1p0_mac_postamble[][5] = {
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
};
static const u32 ar9480_1p0_mac_postamble_emulation[][5] = {
static const u32 ar9462_1p0_mac_postamble_emulation[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8},
{0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017},
};
static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = {
static const u32 ar9462_1p0_tx_gain_table_baseband_postamble_emulation[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5},
{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
......@@ -1163,7 +1163,7 @@ static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = {
{0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a},
};
static const u32 ar9480_1p0_radio_postamble[][5] = {
static const u32 ar9462_1p0_radio_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
{0x000160ac, 0xa4646c08, 0xa4646c08, 0x24646c08, 0x24646c08},
......@@ -1174,12 +1174,12 @@ static const u32 ar9480_1p0_radio_postamble[][5] = {
{0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
};
static const u32 ar9480_1p0_soc_postamble_emulation[][5] = {
static const u32 ar9462_1p0_soc_postamble_emulation[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00007010, 0x00001133, 0x00001133, 0x00001133, 0x00001133},
};
static const u32 ar9480_1p0_baseband_core[][2] = {
static const u32 ar9462_1p0_baseband_core[][2] = {
/* Addr allmodes */
{0x00009800, 0xafe68e30},
{0x00009804, 0xfd14e000},
......@@ -1336,7 +1336,7 @@ static const u32 ar9480_1p0_baseband_core[][2] = {
{0x0000b6b4, 0x00c00001},
};
static const u32 ar9480_1p0_baseband_postamble[][5] = {
static const u32 ar9462_1p0_baseband_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
......@@ -1386,7 +1386,7 @@ static const u32 ar9480_1p0_baseband_postamble[][5] = {
{0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
};
static const u32 ar9480_modes_fast_clock_1p0[][3] = {
static const u32 ar9462_modes_fast_clock_1p0[][3] = {
/* Addr 5G_HT20 5G_HT40 */
{0x00001030, 0x00000268, 0x000004d0},
{0x00001070, 0x0000018c, 0x00000318},
......@@ -1399,7 +1399,7 @@ static const u32 ar9480_modes_fast_clock_1p0[][3] = {
{0x0000a254, 0x00000898, 0x00001130},
};
static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = {
static const u32 ar9462_modes_low_ob_db_tx_gain_table_1p0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
{0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
......@@ -1464,12 +1464,12 @@ static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = {
{0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
};
static const u32 ar9480_1p0_soc_postamble[][5] = {
static const u32 ar9462_1p0_soc_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233},
};
static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = {
static const u32 ar9462_common_mixed_rx_gain_table_1p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
......@@ -1729,14 +1729,14 @@ static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = {
{0x0000b1fc, 0x00000196},
};
static const u32 ar9480_pcie_phy_clkreq_disable_L1_1p0[][2] = {
static const u32 ar9462_pcie_phy_clkreq_disable_L1_1p0[][2] = {
/* Addr allmodes */
{0x00018c00, 0x10013e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000580c},
};
static const u32 ar9480_1p0_baseband_core_emulation[][2] = {
static const u32 ar9462_1p0_baseband_core_emulation[][2] = {
/* Addr allmodes */
{0x00009800, 0xafa68e30},
{0x00009884, 0x00002842},
......@@ -1758,7 +1758,7 @@ static const u32 ar9480_1p0_baseband_core_emulation[][2] = {
{0x0000a690, 0x00000038},
};
static const u32 ar9480_1p0_radio_core[][2] = {
static const u32 ar9462_1p0_radio_core[][2] = {
/* Addr allmodes */
{0x00016000, 0x36db6db6},
{0x00016004, 0x6db6db40},
......@@ -1818,16 +1818,16 @@ static const u32 ar9480_1p0_radio_core[][2] = {
{0x00016548, 0x000080c0},
};
static const u32 ar9480_1p0_soc_preamble[][2] = {
static const u32 ar9462_1p0_soc_preamble[][2] = {
/* Addr allmodes */
{0x00007020, 0x00000000},
{0x00007034, 0x00000002},
{0x00007038, 0x000004c2},
};
static const u32 ar9480_1p0_sys2ant[][2] = {
static const u32 ar9462_1p0_sys2ant[][2] = {
/* Addr allmodes */
{0x00063120, 0x00801980},
};
#endif /* INITVALS_9480_1P0_H */
#endif /* INITVALS_9462_1P0_H */
drivers/net/wireless/ath/ath9k/ar9480_2p0_initvals.h → drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
浏览文件 @ 41ebe9cd
......@@ -14,12 +14,12 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef INITVALS_9480_2P0_H
#define INITVALS_9480_2P0_H
#ifndef INITVALS_9462_2P0_H
#define INITVALS_9462_2P0_H
/* AR9480 2.0 */
/* AR9462 2.0 */
static const u32 ar9480_modes_fast_clock_2p0[][3] = {
static const u32 ar9462_modes_fast_clock_2p0[][3] = {
/* Addr 5G_HT20 5G_HT40 */
{0x00001030, 0x00000268, 0x000004d0},
{0x00001070, 0x0000018c, 0x00000318},
......@@ -32,14 +32,14 @@ static const u32 ar9480_modes_fast_clock_2p0[][3] = {
{0x0000a254, 0x00000898, 0x00001130},
};
static const u32 ar9480_pciephy_clkreq_enable_L1_2p0[][2] = {
static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18253ede},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0003580c},
};
static const u32 ar9480_2p0_baseband_postamble[][5] = {
static const u32 ar9462_2p0_baseband_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
......@@ -89,7 +89,7 @@ static const u32 ar9480_2p0_baseband_postamble[][5] = {
{0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
};
static const u32 ar9480_2p0_mac_core_emulation[][2] = {
static const u32 ar9462_2p0_mac_core_emulation[][2] = {
/* Addr allmodes */
{0x00000030, 0x000e0085},
{0x00000044, 0x00000008},
......@@ -97,7 +97,7 @@ static const u32 ar9480_2p0_mac_core_emulation[][2] = {
{0x00008344, 0xaa4a105b},
};
static const u32 ar9480_common_rx_gain_table_2p0[][2] = {
static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
......@@ -357,27 +357,27 @@ static const u32 ar9480_common_rx_gain_table_2p0[][2] = {
{0x0000b1fc, 0x00000196},
};
static const u32 ar9480_pciephy_clkreq_disable_L1_2p0[][2] = {
static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18213ede},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0003580c},
};
static const u32 ar9480_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18212ede},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0003580c},
};
static const u32 ar9480_2p0_sys3ant[][2] = {
static const u32 ar9462_2p0_sys3ant[][2] = {
/* Addr allmodes */
{0x00063280, 0x00040807},
{0x00063284, 0x104ccccc},
};
static const u32 ar9480_common_rx_gain_table_ar9280_2p0[][2] = {
static const u32 ar9462_common_rx_gain_table_ar9280_2p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x02000101},
{0x0000a004, 0x02000102},
......@@ -679,20 +679,20 @@ static const u32 ar9200_ar9280_2p0_radio_core[][2] = {
{0x00007894, 0x5a108000},
};
static const u32 ar9480_2p0_mac_postamble_emulation[][5] = {
static const u32 ar9462_2p0_mac_postamble_emulation[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8},
{0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017},
};
static const u32 ar9480_2p0_radio_postamble_sys3ant[][5] = {
static const u32 ar9462_2p0_radio_postamble_sys3ant[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
{0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
{0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
};
static const u32 ar9480_2p0_baseband_postamble_emulation[][5] = {
static const u32 ar9462_2p0_baseband_postamble_emulation[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221},
......@@ -714,14 +714,14 @@ static const u32 ar9480_2p0_baseband_postamble_emulation[][5] = {
{0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
};
static const u32 ar9480_2p0_radio_postamble_sys2ant[][5] = {
static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
{0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
{0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
};
static const u32 ar9480_common_wo_xlna_rx_gain_table_2p0[][2] = {
static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
......@@ -981,14 +981,14 @@ static const u32 ar9480_common_wo_xlna_rx_gain_table_2p0[][2] = {
{0x0000b1fc, 0x00000196},
};
static const u32 ar9480_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
/* Addr allmodes */
{0x0000a398, 0x00000000},
{0x0000a39c, 0x6f7f0301},
{0x0000a3a0, 0xca9228ee},
};
static const u32 ar9480_modes_low_ob_db_tx_gain_table_2p0[][5] = {
static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
{0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
......@@ -1057,12 +1057,12 @@ static const u32 ar9480_modes_low_ob_db_tx_gain_table_2p0[][5] = {
{0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
};
static const u32 ar9480_2p0_soc_postamble[][5] = {
static const u32 ar9462_2p0_soc_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233},
};
static const u32 ar9480_2p0_baseband_core[][2] = {
static const u32 ar9462_2p0_baseband_core[][2] = {
/* Addr allmodes */
{0x00009800, 0xafe68e30},
{0x00009804, 0xfd14e000},
......@@ -1221,7 +1221,7 @@ static const u32 ar9480_2p0_baseband_core[][2] = {
{0x0000b6b4, 0x00000001},
};
static const u32 ar9480_2p0_radio_postamble[][5] = {
static const u32 ar9462_2p0_radio_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
{0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
......@@ -1229,7 +1229,7 @@ static const u32 ar9480_2p0_radio_postamble[][5] = {
{0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
};
static const u32 ar9480_modes_high_ob_db_tx_gain_table_2p0[][5] = {
static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
{0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
......@@ -1298,7 +1298,7 @@ static const u32 ar9480_modes_high_ob_db_tx_gain_table_2p0[][5] = {
{0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
};
static const u32 ar9480_2p0_radio_core[][2] = {
static const u32 ar9462_2p0_radio_core[][2] = {
/* Addr allmodes */
{0x00016000, 0x36db6db6},
{0x00016004, 0x6db6db40},
......@@ -1356,7 +1356,7 @@ static const u32 ar9480_2p0_radio_core[][2] = {
{0x00016548, 0x000080c0},
};
static const u32 ar9480_2p0_tx_gain_table_baseband_postamble_emulation[][5] = {
static const u32 ar9462_2p0_tx_gain_table_baseband_postamble_emulation[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5},
{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
......@@ -1374,19 +1374,19 @@ static const u32 ar9480_2p0_tx_gain_table_baseband_postamble_emulation[][5] = {
{0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a},
};
static const u32 ar9480_2p0_soc_preamble[][2] = {
static const u32 ar9462_2p0_soc_preamble[][2] = {
/* Addr allmodes */
{0x00007020, 0x00000000},
{0x00007034, 0x00000002},
{0x00007038, 0x000004c2},
};
static const u32 ar9480_2p0_sys2ant[][2] = {
static const u32 ar9462_2p0_sys2ant[][2] = {
/* Addr allmodes */
{0x00063120, 0x00801980},
};
static const u32 ar9480_2p0_mac_core[][2] = {
static const u32 ar9462_2p0_mac_core[][2] = {
/* Addr allmodes */
{0x00000008, 0x00000000},
{0x00000030, 0x000e0085},
......@@ -1550,7 +1550,7 @@ static const u32 ar9480_2p0_mac_core[][2] = {
{0x000083d0, 0x000301ff},
};
static const u32 ar9480_2p0_mac_postamble[][5] = {
static const u32 ar9462_2p0_mac_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
......@@ -1562,7 +1562,7 @@ static const u32 ar9480_2p0_mac_postamble[][5] = {
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
};
static const u32 ar9480_common_mixed_rx_gain_table_2p0[][2] = {
static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
......@@ -1822,7 +1822,7 @@ static const u32 ar9480_common_mixed_rx_gain_table_2p0[][2] = {
{0x0000b1fc, 0x00000196},
};
static const u32 ar9480_modes_green_ob_db_tx_gain_table_2p0[][5] = {
static const u32 ar9462_modes_green_ob_db_tx_gain_table_2p0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
{0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
......@@ -1891,7 +1891,7 @@ static const u32 ar9480_modes_green_ob_db_tx_gain_table_2p0[][5] = {
{0x00016454, 0x6db60180, 0x6db60180, 0x6db60180, 0x6db60180},
};
static const u32 ar9480_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
static const u32 ar9462_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
/* Addr allmodes */
{0x000018c0, 0x10101010},
{0x000018c4, 0x10101010},
......@@ -1903,7 +1903,7 @@ static const u32 ar9480_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
{0x000018dc, 0x10101010},
};
static const u32 ar9480_2p0_baseband_core_emulation[][2] = {
static const u32 ar9462_2p0_baseband_core_emulation[][2] = {
/* Addr allmodes */
{0x00009800, 0xafa68e30},
{0x00009884, 0x00002842},
......@@ -1925,4 +1925,4 @@ static const u32 ar9480_2p0_baseband_core_emulation[][2] = {
{0x0000a690, 0x00000038},
};
#endif /* INITVALS_9480_2P0_H */
#endif /* INITVALS_9462_2P0_H */
drivers/net/wireless/ath/ath9k/ath9k.h
浏览文件 @ 41ebe9cd
......@@ -458,7 +458,7 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc);
#define ATH_LED_PIN_9287 8
#define ATH_LED_PIN_9300 10
#define ATH_LED_PIN_9485 6
#define ATH_LED_PIN_9480 0
#define ATH_LED_PIN_9462 0
#ifdef CONFIG_MAC80211_LEDS
void ath_init_leds(struct ath_softc *sc);
......
drivers/net/wireless/ath/ath9k/beacon.c
浏览文件 @ 41ebe9cd
......@@ -515,7 +515,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
sc->sc_flags |= SC_OP_TSF_RESET;
ath9k_beacon_init(sc, nexttbtt, intval);
sc->beacon.bmisscnt = 0;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
ath9k_hw_enable_interrupts(ah);
}
......@@ -643,7 +643,7 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
ath9k_hw_set_sta_beacon_timers(ah, &bs);
ah->imask |= ATH9K_INT_BMISS;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
ath9k_hw_enable_interrupts(ah);
}
......@@ -679,7 +679,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
ath9k_beacon_init(sc, nexttbtt, intval);
sc->beacon.bmisscnt = 0;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
ath9k_hw_enable_interrupts(ah);
}
......@@ -821,11 +821,11 @@ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
if (status) {
/* Re-enable beaconing */
ah->imask |= ATH9K_INT_SWBA;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
} else {
/* Disable SWBA interrupt */
ah->imask &= ~ATH9K_INT_SWBA;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
tasklet_kill(&sc->bcon_tasklet);
ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
}
......
drivers/net/wireless/ath/ath9k/common.c
浏览文件 @ 41ebe9cd
......@@ -161,10 +161,12 @@ EXPORT_SYMBOL(ath9k_cmn_count_streams);
void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
u16 new_txpow, u16 *txpower)
{
if (cur_txpow != new_txpow) {
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
if (reg->power_limit != new_txpow) {
ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
/* read back in case value is clamped */
*txpower = ath9k_hw_regulatory(ah)->power_limit;
*txpower = reg->max_power_level;
}
}
EXPORT_SYMBOL(ath9k_cmn_update_txpow);
......
drivers/net/wireless/ath/ath9k/debug.c
浏览文件 @ 41ebe9cd
......@@ -523,9 +523,22 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
if (tmp & ATH9K_RX_FILTER_PHYRADAR)
len += snprintf(buf + len, sizeof(buf) - len, " PHYRADAR");
if (tmp & ATH9K_RX_FILTER_MCAST_BCAST_ALL)
len += snprintf(buf + len, sizeof(buf) - len, " MCAST_BCAST_ALL\n");
else
len += snprintf(buf + len, sizeof(buf) - len, "\n");
len += snprintf(buf + len, sizeof(buf) - len, " MCAST_BCAST_ALL");
len += snprintf(buf + len, sizeof(buf) - len,
"\n\nReset causes:\n"
" baseband hang: %d\n"
" baseband watchdog: %d\n"
" fatal hardware error interrupt: %d\n"
" tx hardware error: %d\n"
" tx path hang: %d\n"
" pll rx hang: %d\n",
sc->debug.stats.reset[RESET_TYPE_BB_HANG],
sc->debug.stats.reset[RESET_TYPE_BB_WATCHDOG],
sc->debug.stats.reset[RESET_TYPE_FATAL_INT],
sc->debug.stats.reset[RESET_TYPE_TX_ERROR],
sc->debug.stats.reset[RESET_TYPE_TX_HANG],
sc->debug.stats.reset[RESET_TYPE_PLL_HANG]);
if (len > sizeof(buf))
len = sizeof(buf);
......
drivers/net/wireless/ath/ath9k/debug.h
浏览文件 @ 41ebe9cd
......@@ -25,8 +25,10 @@ struct ath_buf;
#ifdef CONFIG_ATH9K_DEBUGFS
#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
#else
#define TX_STAT_INC(q, c) do { } while (0)
#define RESET_STAT_INC(sc, type) do { } while (0)
#endif
#ifdef CONFIG_ATH9K_DEBUGFS
......@@ -171,10 +173,21 @@ struct ath_rx_stats {
u8 rs_antenna;
};
enum ath_reset_type {
RESET_TYPE_BB_HANG,
RESET_TYPE_BB_WATCHDOG,
RESET_TYPE_FATAL_INT,
RESET_TYPE_TX_ERROR,
RESET_TYPE_TX_HANG,
RESET_TYPE_PLL_HANG,
__RESET_TYPE_MAX
};
struct ath_stats {
struct ath_interrupt_stats istats;
struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
struct ath_rx_stats rxstats;
u32 reset[__RESET_TYPE_MAX];
};
#define ATH_DBG_MAX_SAMPLES 10
......
drivers/net/wireless/ath/ath9k/eeprom.h
浏览文件 @ 41ebe9cd
......@@ -108,7 +108,7 @@
#define EEP_RFSILENT_ENABLED_S 0
#define EEP_RFSILENT_POLARITY 0x0002
#define EEP_RFSILENT_POLARITY_S 1
#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9480(ah) ? 0x00fc : 0x001c)
#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9462(ah) ? 0x00fc : 0x001c)
#define EEP_RFSILENT_GPIO_SEL_S 2
#define AR5416_OPFLAGS_11A 0x01
......@@ -220,7 +220,6 @@ enum eeprom_param {
EEP_MAC_MID,
EEP_MAC_LSW,
EEP_REG_0,
EEP_REG_1,
EEP_OP_CAP,
EEP_OP_MODE,
EEP_RF_SILENT,
......@@ -248,7 +247,9 @@ enum eeprom_param {
EEP_PAPRD,
EEP_MODAL_VER,
EEP_ANT_DIV_CTL1,
EEP_CHAIN_MASK_REDUCE
EEP_CHAIN_MASK_REDUCE,
EEP_ANTENNA_GAIN_2G,
EEP_ANTENNA_GAIN_5G
};
enum ar5416_rates {
......@@ -652,8 +653,7 @@ struct eeprom_ops {
void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
u16 cfgCtl, u8 twiceAntennaReduction,
u8 twiceMaxRegulatoryPower, u8 powerLimit,
bool test);
u8 powerLimit, bool test);
u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
};
......
drivers/net/wireless/ath/ath9k/eeprom_4k.c
浏览文件 @ 41ebe9cd
......@@ -322,8 +322,6 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
return get_unaligned_be16(pBase->macAddr + 4);
case EEP_REG_0:
return pBase->regDmn[0];
case EEP_REG_1:
return pBase->regDmn[1];
case EEP_OP_CAP:
return pBase->deviceCap;
case EEP_OP_MODE:
......@@ -350,6 +348,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
return pModal->antdiv_ctl1;
case EEP_TXGAIN_TYPE:
return pBase->txGainType;
case EEP_ANTENNA_GAIN_2G:
return pModal->antennaGainCh[0];
default:
return 0;
}
......@@ -462,8 +462,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
struct ath9k_channel *chan,
int16_t *ratesArray,
u16 cfgCtl,
u16 AntennaReduction,
u16 twiceMaxRegulatoryPower,
u16 antenna_reduction,
u16 powerLimit)
{
#define CMP_TEST_GRP \
......@@ -472,20 +471,16 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
|| (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
int i;
int16_t twiceLargestAntenna;
u16 twiceMinEdgePower;
u16 twiceMaxEdgePower = MAX_RATE_POWER;
u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
u16 scaledPower = 0, minCtlPower;
u16 numCtlModes;
const u16 *pCtlMode;
u16 ctlMode, freq;
struct chan_centers centers;
struct cal_ctl_data_4k *rep;
struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
static const u16 tpScaleReductionTable[5] =
{ 0, 3, 6, 9, MAX_RATE_POWER };
struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
0, { 0, 0, 0, 0}
};
......@@ -503,19 +498,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
ath9k_hw_get_channel_centers(ah, chan, &centers);
twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
twiceLargestAntenna = (int16_t)min(AntennaReduction -
twiceLargestAntenna, 0);
maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
maxRegAllowedPower -=
(tpScaleReductionTable[(regulatory->tp_scale)] * 2);
}
scaledPower = min(powerLimit, maxRegAllowedPower);
scaledPower = max((u16)0, scaledPower);
scaledPower = powerLimit - antenna_reduction;
numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
pCtlMode = ctlModesFor11g;
......@@ -671,7 +654,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
struct ath9k_channel *chan,
u16 cfgCtl,
u8 twiceAntennaReduction,
u8 twiceMaxRegulatoryPower,
u8 powerLimit, bool test)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
......@@ -691,7 +673,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
ath9k_hw_set_4k_power_per_rate_table(ah, chan,
&ratesArray[0], cfgCtl,
twiceAntennaReduction,
twiceMaxRegulatoryPower,
powerLimit);
ath9k_hw_set_4k_power_cal_table(ah, chan);
......
drivers/net/wireless/ath/ath9k/eeprom_9287.c
浏览文件 @ 41ebe9cd
......@@ -308,8 +308,6 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
return get_unaligned_be16(pBase->macAddr + 4);
case EEP_REG_0:
return pBase->regDmn[0];
case EEP_REG_1:
return pBase->regDmn[1];
case EEP_OP_CAP:
return pBase->deviceCap;
case EEP_OP_MODE:
......@@ -336,6 +334,9 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
return pBase->tempSensSlopePalOn;
else
return 0;
case EEP_ANTENNA_GAIN_2G:
return max_t(u8, pModal->antennaGainCh[0],
pModal->antennaGainCh[1]);
default:
return 0;
}
......@@ -554,8 +555,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
struct ath9k_channel *chan,
int16_t *ratesArray,
u16 cfgCtl,
u16 AntennaReduction,
u16 twiceMaxRegulatoryPower,
u16 antenna_reduction,
u16 powerLimit)
{
#define CMP_CTL \
......@@ -569,12 +569,8 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
u16 twiceMaxEdgePower = MAX_RATE_POWER;
static const u16 tpScaleReductionTable[5] =
{ 0, 3, 6, 9, MAX_RATE_POWER };
int i;
int16_t twiceLargestAntenna;
struct cal_ctl_data_ar9287 *rep;
struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
targetPowerCck = {0, {0, 0, 0, 0} };
......@@ -582,7 +578,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
targetPowerCckExt = {0, {0, 0, 0, 0} };
struct cal_target_power_ht targetPowerHt20,
targetPowerHt40 = {0, {0, 0, 0, 0} };
u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
u16 scaledPower = 0, minCtlPower;
static const u16 ctlModesFor11g[] = {
CTL_11B, CTL_11G, CTL_2GHT20,
CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
......@@ -597,24 +593,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
tx_chainmask = ah->txchainmask;
ath9k_hw_get_channel_centers(ah, chan, &centers);
/* Compute TxPower reduction due to Antenna Gain */
twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
pEepData->modalHeader.antennaGainCh[1]);
twiceLargestAntenna = (int16_t)min((AntennaReduction) -
twiceLargestAntenna, 0);
/*
* scaledPower is the minimum of the user input power level
* and the regulatory allowed power level.
*/
maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
maxRegAllowedPower -=
(tpScaleReductionTable[(regulatory->tp_scale)] * 2);
scaledPower = min(powerLimit, maxRegAllowedPower);
scaledPower = powerLimit - antenna_reduction;
/*
* Reduce scaled Power by number of chains active
......@@ -815,7 +794,6 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
struct ath9k_channel *chan, u16 cfgCtl,
u8 twiceAntennaReduction,
u8 twiceMaxRegulatoryPower,
u8 powerLimit, bool test)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
......@@ -834,7 +812,6 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
&ratesArray[0], cfgCtl,
twiceAntennaReduction,
twiceMaxRegulatoryPower,
powerLimit);
ath9k_hw_set_ar9287_power_cal_table(ah, chan);
......
drivers/net/wireless/ath/ath9k/eeprom_def.c
浏览文件 @ 41ebe9cd
......@@ -400,6 +400,7 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
struct ar5416_eeprom_def *eep = &ah->eeprom.def;
struct modal_eep_header *pModal = eep->modalHeader;
struct base_eep_header *pBase = &eep->baseEepHeader;
int band = 0;
switch (param) {
case EEP_NFTHRESH_5:
......@@ -414,8 +415,6 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
return get_unaligned_be16(pBase->macAddr + 4);
case EEP_REG_0:
return pBase->regDmn[0];
case EEP_REG_1:
return pBase->regDmn[1];
case EEP_OP_CAP:
return pBase->deviceCap;
case EEP_OP_MODE:
......@@ -467,6 +466,14 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
return pBase->pwr_table_offset;
else
return AR5416_PWR_TABLE_OFFSET_DB;
case EEP_ANTENNA_GAIN_2G:
band = 1;
/* fall through */
case EEP_ANTENNA_GAIN_5G:
return max_t(u8, max_t(u8,
pModal[band].antennaGainCh[0],
pModal[band].antennaGainCh[1]),
pModal[band].antennaGainCh[2]);
default:
return 0;
}
......@@ -986,21 +993,15 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
struct ath9k_channel *chan,
int16_t *ratesArray,
u16 cfgCtl,
u16 AntennaReduction,
u16 twiceMaxRegulatoryPower,
u16 antenna_reduction,
u16 powerLimit)
{
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
u16 twiceMaxEdgePower = MAX_RATE_POWER;
static const u16 tpScaleReductionTable[5] =
{ 0, 3, 6, 9, MAX_RATE_POWER };
int i;
int16_t twiceLargestAntenna;
struct cal_ctl_data *rep;
struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
0, { 0, 0, 0, 0}
......@@ -1012,7 +1013,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
0, {0, 0, 0, 0}
};
u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
u16 scaledPower = 0, minCtlPower;
static const u16 ctlModesFor11a[] = {
CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
};
......@@ -1031,27 +1032,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
ath9k_hw_get_channel_centers(ah, chan, &centers);
twiceLargestAntenna = max(
pEepData->modalHeader
[IS_CHAN_2GHZ(chan)].antennaGainCh[0],
pEepData->modalHeader
[IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
twiceLargestAntenna = max((u8)twiceLargestAntenna,
pEepData->modalHeader
[IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
twiceLargestAntenna = (int16_t)min(AntennaReduction -
twiceLargestAntenna, 0);
maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
maxRegAllowedPower -=
(tpScaleReductionTable[(regulatory->tp_scale)] * 2);
}
scaledPower = min(powerLimit, maxRegAllowedPower);
scaledPower = powerLimit - antenna_reduction;
switch (ar5416_get_ntxchains(tx_chainmask)) {
case 1:
......@@ -1256,7 +1237,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
struct ath9k_channel *chan,
u16 cfgCtl,
u8 twiceAntennaReduction,
u8 twiceMaxRegulatoryPower,
u8 powerLimit, bool test)
{
#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
......@@ -1278,7 +1258,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
ath9k_hw_set_def_power_per_rate_table(ah, chan,
&ratesArray[0], cfgCtl,
twiceAntennaReduction,
twiceMaxRegulatoryPower,
powerLimit);
ath9k_hw_set_def_power_cal_table(ah, chan);
......
drivers/net/wireless/ath/ath9k/gpio.c
浏览文件 @ 41ebe9cd
......@@ -48,8 +48,8 @@ void ath_init_leds(struct ath_softc *sc)
sc->sc_ah->led_pin = ATH_LED_PIN_9485;
else if (AR_SREV_9300(sc->sc_ah))
sc->sc_ah->led_pin = ATH_LED_PIN_9300;
else if (AR_SREV_9480(sc->sc_ah))
sc->sc_ah->led_pin = ATH_LED_PIN_9480;
else if (AR_SREV_9462(sc->sc_ah))
sc->sc_ah->led_pin = ATH_LED_PIN_9462;
else
sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
}
......@@ -155,7 +155,7 @@ static void ath9k_gen_timer_start(struct ath_hw *ah,
if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
ath9k_hw_disable_interrupts(ah);
ah->imask |= ATH9K_INT_GENTIMER;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
ath9k_hw_enable_interrupts(ah);
}
}
......@@ -170,7 +170,7 @@ static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
if (timer_table->timer_mask.val == 0) {
ath9k_hw_disable_interrupts(ah);
ah->imask &= ~ATH9K_INT_GENTIMER;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
ath9k_hw_enable_interrupts(ah);
}
}
......
drivers/net/wireless/ath/ath9k/hw-ops.h
浏览文件 @ 41ebe9cd
......@@ -205,4 +205,11 @@ static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
}
static inline int ath9k_hw_fast_chan_change(struct ath_hw *ah,
struct ath9k_channel *chan,
u8 *ini_reloaded)
{
return ath9k_hw_private_ops(ah)->fast_chan_change(ah, chan,
ini_reloaded);
}
#endif /* ATH9K_HW_OPS_H */
drivers/net/wireless/ath/ath9k/hw.c
浏览文件 @ 41ebe9cd
......@@ -285,7 +285,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
if (AR_SREV_9480(ah))
if (AR_SREV_9462(ah))
ah->is_pciexpress = true;
else
ah->is_pciexpress = (val &
......@@ -433,7 +433,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
regulatory->country_code = CTRY_DEFAULT;
regulatory->power_limit = MAX_RATE_POWER;
regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
ah->hw_version.magic = AR5416_MAGIC;
ah->hw_version.subvendorid = 0;
......@@ -542,6 +541,9 @@ static int __ath9k_hw_init(struct ath_hw *ah)
return -EIO;
}
if (AR_SREV_9462(ah))
ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
ath9k_hw_init_defaults(ah);
ath9k_hw_init_config(ah);
......@@ -585,7 +587,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
case AR_SREV_VERSION_9330:
case AR_SREV_VERSION_9485:
case AR_SREV_VERSION_9340:
case AR_SREV_VERSION_9480:
case AR_SREV_VERSION_9462:
break;
default:
ath_err(common,
......@@ -670,7 +672,7 @@ int ath9k_hw_init(struct ath_hw *ah)
case AR9300_DEVID_AR9330:
case AR9300_DEVID_AR9340:
case AR9300_DEVID_AR9580:
case AR9300_DEVID_AR9480:
case AR9300_DEVID_AR9462:
break;
default:
if (common->bus_ops->ath_bus_type == ATH_USB)
......@@ -1389,11 +1391,17 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
static bool ath9k_hw_channel_change(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath_common *common = ath9k_hw_common(ah);
struct ieee80211_channel *channel = chan->chan;
u32 qnum;
int r;
bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
bool band_switch, mode_diff;
u8 ini_reloaded;
band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
(ah->curchan->channelFlags & (CHANNEL_2GHZ |
CHANNEL_5GHZ));
mode_diff = (chan->chanmode != ah->curchan->chanmode);
for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
if (ath9k_hw_numtxpending(ah, qnum)) {
......@@ -1408,6 +1416,18 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
return false;
}
if (edma && (band_switch || mode_diff)) {
ath9k_hw_mark_phy_inactive(ah);
udelay(5);
ath9k_hw_init_pll(ah, NULL);
if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
ath_err(common, "Failed to do fast channel change\n");
return false;
}
}
ath9k_hw_set_channel_regs(ah, chan);
r = ath9k_hw_rf_set_freq(ah, chan);
......@@ -1416,14 +1436,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
return false;
}
ath9k_hw_set_clockrate(ah);
ah->eep_ops->set_txpower(ah, chan,
ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2,
channel->max_power * 2,
min((u32) MAX_RATE_POWER,
(u32) regulatory->power_limit), false);
ath9k_hw_apply_txpower(ah, chan);
ath9k_hw_rfbus_done(ah);
if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
......@@ -1431,6 +1444,18 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
ath9k_hw_spur_mitigate_freq(ah, chan);
if (edma && (band_switch || mode_diff)) {
ah->ah_flags |= AH_FASTCC;
if (band_switch || ini_reloaded)
ah->eep_ops->set_board_values(ah, chan);
ath9k_hw_init_bb(ah, chan);
if (band_switch || ini_reloaded)
ath9k_hw_init_cal(ah, chan);
ah->ah_flags &= ~AH_FASTCC;
}
return true;
}
......@@ -1486,6 +1511,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
u32 macStaId1;
u64 tsf = 0;
int i, r;
bool allow_fbs = false;
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
return -EIO;
......@@ -1504,16 +1530,22 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
}
ah->noise = ath9k_hw_getchan_noise(ah, chan);
if ((AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) ||
(AR_SREV_9300_20_OR_LATER(ah) && IS_CHAN_5GHZ(chan)))
if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
bChannelChange = false;
if (caldata &&
caldata->done_txiqcal_once &&
caldata->done_txclcal_once &&
caldata->rtt_hist.num_readings)
allow_fbs = true;
if (bChannelChange &&
(ah->chip_fullsleep != true) &&
(ah->curchan != NULL) &&
(chan->channel != ah->curchan->channel) &&
((chan->channelFlags & CHANNEL_ALL) ==
(ah->curchan->channelFlags & CHANNEL_ALL))) {
(allow_fbs ||
((chan->channelFlags & CHANNEL_ALL) ==
(ah->curchan->channelFlags & CHANNEL_ALL)))) {
if (ath9k_hw_channel_change(ah, chan)) {
ath9k_hw_loadnf(ah, ah->curchan);
ath9k_hw_start_nfcal(ah, true);
......@@ -1684,6 +1716,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ath9k_hw_init_bb(ah, chan);
if (caldata) {
caldata->done_txiqcal_once = false;
caldata->done_txclcal_once = false;
caldata->rtt_hist.num_readings = 0;
}
if (!ath9k_hw_init_cal(ah, chan))
return -EIO;
......@@ -1753,7 +1790,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
{
REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
if (setChip) {
if (AR_SREV_9480(ah)) {
if (AR_SREV_9462(ah)) {
REG_WRITE(ah, AR_TIMER_MODE,
REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
......@@ -1771,7 +1808,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
*/
REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
if (AR_SREV_9480(ah))
if (AR_SREV_9462(ah))
udelay(100);
if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
......@@ -1779,15 +1816,14 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
/* Shutdown chip. Active low */
if (!AR_SREV_5416(ah) &&
!AR_SREV_9271(ah) && !AR_SREV_9480_10(ah)) {
!AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) {
REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
udelay(2);
}
}
/* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
if (!AR_SREV_9480(ah))
REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
}
/*
......@@ -1818,7 +1854,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
* SYS_WAKING and SYS_SLEEPING messages which will make
* BT CPU to busy to process.
*/
if (AR_SREV_9480(ah)) {
if (AR_SREV_9462(ah)) {
val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
......@@ -1830,7 +1866,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
AR_RTC_FORCE_WAKE_EN);
if (AR_SREV_9480(ah))
if (AR_SREV_9462(ah))
udelay(30);
}
}
......@@ -2082,11 +2118,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
regulatory->current_rd = eeval;
eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
if (AR_SREV_9285_12_OR_LATER(ah))
eeval |= AR9285_RDEXT_DEFAULT;
regulatory->current_rd_ext = eeval;
if (ah->opmode != NL80211_IFTYPE_AP &&
ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
if (regulatory->current_rd == 0x64 ||
......@@ -2294,6 +2325,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
rx_chainmask >>= 1;
}
if (AR_SREV_9300_20_OR_LATER(ah)) {
ah->enabled_cals |= TX_IQ_CAL;
if (!AR_SREV_9330(ah))
ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
}
if (AR_SREV_9462(ah))
pCap->hw_caps |= ATH9K_HW_CAP_RTT;
return 0;
}
......@@ -2454,7 +2493,7 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
ENABLE_REGWRITE_BUFFER(ah);
if (AR_SREV_9480(ah))
if (AR_SREV_9462(ah))
bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
REG_WRITE(ah, AR_RX_FILTER, bits);
......@@ -2498,23 +2537,56 @@ bool ath9k_hw_disable(struct ath_hw *ah)
}
EXPORT_SYMBOL(ath9k_hw_disable);
static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
{
enum eeprom_param gain_param;
if (IS_CHAN_2GHZ(chan))
gain_param = EEP_ANTENNA_GAIN_2G;
else
gain_param = EEP_ANTENNA_GAIN_5G;
return ah->eep_ops->get_eeprom(ah, gain_param);
}
void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
{
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
struct ieee80211_channel *channel;
int chan_pwr, new_pwr, max_gain;
int ant_gain, ant_reduction = 0;
if (!chan)
return;
channel = chan->chan;
chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
new_pwr = min_t(int, chan_pwr, reg->power_limit);
max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
ant_gain = get_antenna_gain(ah, chan);
if (ant_gain > max_gain)
ant_reduction = ant_gain - max_gain;
ah->eep_ops->set_txpower(ah, chan,
ath9k_regd_get_ctl(reg, chan),
ant_reduction, new_pwr, false);
}
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
struct ath9k_channel *chan = ah->curchan;
struct ieee80211_channel *channel = chan->chan;
int reg_pwr = min_t(int, MAX_RATE_POWER, limit);
int chan_pwr = channel->max_power * 2;
reg->power_limit = min_t(int, limit, MAX_RATE_POWER);
if (test)
reg_pwr = chan_pwr = MAX_RATE_POWER;
channel->max_power = MAX_RATE_POWER / 2;
regulatory->power_limit = reg_pwr;
ath9k_hw_apply_txpower(ah, chan);
ah->eep_ops->set_txpower(ah, chan,
ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2,
chan_pwr, reg_pwr, test);
if (test)
channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
}
EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
......@@ -2713,9 +2785,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
gen_tmr_configuration[timer->index].mode_mask);
if (AR_SREV_9480(ah)) {
if (AR_SREV_9462(ah)) {
/*
* Starting from AR9480, each generic timer can select which tsf
* Starting from AR9462, each generic timer can select which tsf
* to use. But we still follow the old rule, 0 - 7 use tsf and
* 8 - 15 use tsf2.
*/
......@@ -2832,7 +2904,7 @@ static struct {
{ AR_SREV_VERSION_9330, "9330" },
{ AR_SREV_VERSION_9340, "9340" },
{ AR_SREV_VERSION_9485, "9485" },
{ AR_SREV_VERSION_9480, "9480" },
{ AR_SREV_VERSION_9462, "9462" },
};
/* For devices with external radios */
......
drivers/net/wireless/ath/ath9k/hw.h
浏览文件 @ 41ebe9cd
......@@ -46,7 +46,7 @@
#define AR9300_DEVID_AR9340 0x0031
#define AR9300_DEVID_AR9485_PCIE 0x0032
#define AR9300_DEVID_AR9580 0x0033
#define AR9300_DEVID_AR9480 0x0034
#define AR9300_DEVID_AR9462 0x0034
#define AR9300_DEVID_AR9330 0x0035
#define AR5416_AR9100_DEVID 0x000b
......@@ -202,6 +202,7 @@ enum ath9k_hw_caps {
ATH9K_HW_CAP_2GHZ = BIT(13),
ATH9K_HW_CAP_5GHZ = BIT(14),
ATH9K_HW_CAP_APM = BIT(15),
ATH9K_HW_CAP_RTT = BIT(16),
};
struct ath9k_hw_capabilities {
......@@ -337,6 +338,16 @@ enum ath9k_int {
CHANNEL_HT40PLUS | \
CHANNEL_HT40MINUS)
#define MAX_RTT_TABLE_ENTRY 6
#define RTT_HIST_MAX 3
struct ath9k_rtt_hist {
u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
u8 num_readings;
};
#define MAX_IQCAL_MEASUREMENT 8
#define MAX_CL_TAB_ENTRY 16
struct ath9k_hw_cal_data {
u16 channel;
u32 channelFlags;
......@@ -346,9 +357,15 @@ struct ath9k_hw_cal_data {
bool paprd_done;
bool nfcal_pending;
bool nfcal_interference;
bool done_txiqcal_once;
bool done_txclcal_once;
u16 small_signal_gain[AR9300_MAX_CHAINS];
u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
u32 num_measures[AR9300_MAX_CHAINS];
int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
struct ath9k_rtt_hist rtt_hist;
};
struct ath9k_channel {
......@@ -390,14 +407,6 @@ enum ath9k_power_mode {
ATH9K_PM_UNDEFINED
};
enum ath9k_tp_scale {
ATH9K_TP_SCALE_MAX = 0,
ATH9K_TP_SCALE_50,
ATH9K_TP_SCALE_25,
ATH9K_TP_SCALE_12,
ATH9K_TP_SCALE_MIN
};
enum ser_reg_mode {
SER_REG_MODE_OFF = 0,
SER_REG_MODE_ON = 1,
......@@ -591,6 +600,8 @@ struct ath_hw_private_ops {
void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
void (*set_radar_params)(struct ath_hw *ah,
struct ath_hw_radar_conf *conf);
int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
u8 *ini_reloaded);
/* ANI */
void (*ani_cache_ini_regs)(struct ath_hw *ah);
......@@ -632,9 +643,16 @@ struct ath_nf_limits {
s16 nominal;
};
enum ath_cal_list {
TX_IQ_CAL = BIT(0),
TX_IQ_ON_AGC_CAL = BIT(1),
TX_CL_CAL = BIT(2),
};
/* ah_flags */
#define AH_USE_EEPROM 0x1
#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
#define AH_FASTCC 0x4
struct ath_hw {
struct ath_ops reg_ops;
......@@ -692,6 +710,7 @@ struct ath_hw {
atomic_t intr_ref_cnt;
bool chip_fullsleep;
u32 atim_window;
u32 modes_index;
/* Calibration */
u32 supp_cals;
......@@ -730,6 +749,7 @@ struct ath_hw {
int32_t sign[AR5416_MAX_CHAINS];
} meas3;
u16 cal_samples;
u8 enabled_cals;
u32 sta_id1_defaults;
u32 misc_mode;
......@@ -968,6 +988,7 @@ void ath9k_hw_htc_resetinit(struct ath_hw *ah);
/* PHY */
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
u32 *coef_mantissa, u32 *coef_exponent);
void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
/*
* Code Specific to AR5008, AR9001 or AR9002,
......
drivers/net/wireless/ath/ath9k/init.c
浏览文件 @ 41ebe9cd
......@@ -626,7 +626,6 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
struct ieee80211_supported_band *sband;
struct ieee80211_channel *chan;
struct ath_hw *ah = sc->sc_ah;
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
int i;
sband = &sc->sbands[band];
......@@ -635,7 +634,6 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
ah->curchan = &ah->channels[chan->hw_value];
ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
chan->max_power = reg->max_power_level / 2;
}
}
......
drivers/net/wireless/ath/ath9k/mac.c
浏览文件 @ 41ebe9cd
......@@ -620,8 +620,8 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
rs->rs_status |= ATH9K_RXERR_DECRYPT;
else if (ads.ds_rxstatus8 & AR_MichaelErr)
rs->rs_status |= ATH9K_RXERR_MIC;
else if (ads.ds_rxstatus8 & AR_KeyMiss)
rs->rs_status |= ATH9K_RXERR_DECRYPT;
if (ads.ds_rxstatus8 & AR_KeyMiss)
rs->rs_status |= ATH9K_RXERR_KEYMISS;
}
return 0;
......@@ -827,9 +827,9 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
}
EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
void ath9k_hw_set_interrupts(struct ath_hw *ah)
{
enum ath9k_int omask = ah->imask;
enum ath9k_int ints = ah->imask;
u32 mask, mask2;
struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath_common *common = ath9k_hw_common(ah);
......@@ -837,7 +837,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
if (!(ints & ATH9K_INT_GLOBAL))
ath9k_hw_disable_interrupts(ah);
ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
ath_dbg(common, ATH_DBG_INTERRUPT, "New interrupt mask 0x%x\n", ints);
mask = ints & ATH9K_INT_COMMON;
mask2 = 0;
......
drivers/net/wireless/ath/ath9k/mac.h
浏览文件 @ 41ebe9cd
......@@ -75,9 +75,10 @@
#define ATH9K_TXERR_XTXOP 0x08
#define ATH9K_TXERR_TIMER_EXPIRED 0x10
#define ATH9K_TX_ACKED 0x20
#define ATH9K_TX_FLUSH 0x40
#define ATH9K_TXERR_MASK \
(ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH)
#define ATH9K_TX_BA 0x01
#define ATH9K_TX_PWRMGMT 0x02
......@@ -181,6 +182,7 @@ struct ath_htc_rx_status {
#define ATH9K_RXERR_FIFO 0x04
#define ATH9K_RXERR_DECRYPT 0x08
#define ATH9K_RXERR_MIC 0x10
#define ATH9K_RXERR_KEYMISS 0x20
#define ATH9K_RX_MORE 0x01
#define ATH9K_RX_MORE_AGGR 0x02
......@@ -734,7 +736,7 @@ int ath9k_hw_beaconq_setup(struct ath_hw *ah);
/* Interrupt Handling */
bool ath9k_hw_intrpend(struct ath_hw *ah);
void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
void ath9k_hw_set_interrupts(struct ath_hw *ah);
void ath9k_hw_enable_interrupts(struct ath_hw *ah);
void ath9k_hw_disable_interrupts(struct ath_hw *ah);
......
drivers/net/wireless/ath/ath9k/main.c
浏览文件 @ 41ebe9cd
......@@ -273,7 +273,7 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
ath9k_cmn_update_txpow(ah, sc->curtxpow,
sc->config.txpowlimit, &sc->curtxpow);
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
ath9k_hw_enable_interrupts(ah);
if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
......@@ -679,6 +679,16 @@ void ath9k_tasklet(unsigned long data)
if ((status & ATH9K_INT_FATAL) ||
(status & ATH9K_INT_BB_WATCHDOG)) {
#ifdef CONFIG_ATH9K_DEBUGFS
enum ath_reset_type type;
if (status & ATH9K_INT_FATAL)
type = RESET_TYPE_FATAL_INT;
else
type = RESET_TYPE_BB_WATCHDOG;
RESET_STAT_INC(sc, type);
#endif
ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
goto out;
}
......@@ -823,7 +833,7 @@ irqreturn_t ath_isr(int irq, void *dev)
if (status & ATH9K_INT_RXEOL) {
ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
}
if (status & ATH9K_INT_MIB) {
......@@ -995,8 +1005,10 @@ void ath_hw_check(struct work_struct *work)
ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
"busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
if (busy >= 99) {
if (++sc->hw_busy_count >= 3)
if (++sc->hw_busy_count >= 3) {
RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
}
} else if (busy >= 0)
sc->hw_busy_count = 0;
......@@ -1016,6 +1028,7 @@ static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
/* Rx is hung for more than 500ms. Reset it */
ath_dbg(common, ATH_DBG_RESET,
"Possible RX hang, resetting");
RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
count = 0;
}
......@@ -1396,7 +1409,7 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
ah->imask &= ~ATH9K_INT_TSFOOR;
}
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
/* Set up ANI */
if (iter_data.naps > 0) {
......@@ -1571,7 +1584,7 @@ static void ath9k_enable_ps(struct ath_softc *sc)
if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
ah->imask |= ATH9K_INT_TIM_TIMER;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
}
ath9k_hw_setrxabort(ah, 1);
}
......@@ -1591,7 +1604,7 @@ static void ath9k_disable_ps(struct ath_softc *sc)
PS_WAIT_FOR_TX_ACK);
if (ah->imask & ATH9K_INT_TIM_TIMER) {
ah->imask &= ~ATH9K_INT_TIM_TIMER;
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
}
}
......
drivers/net/wireless/ath/ath9k/pci.c
浏览文件 @ 41ebe9cd
......@@ -33,7 +33,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
{ PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
{ PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9480 */
{ PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
{ 0 }
};
......
drivers/net/wireless/ath/ath9k/recv.c
浏览文件 @ 41ebe9cd
......@@ -433,12 +433,9 @@ void ath_rx_cleanup(struct ath_softc *sc)
u32 ath_calcrxfilter(struct ath_softc *sc)
{
#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
u32 rfilt;
rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
| ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
| ATH9K_RX_FILTER_MCAST;
if (sc->rx.rxfilter & FIF_PROBE_REQ)
......@@ -811,6 +808,7 @@ static bool ath9k_rx_accept(struct ath_common *common,
struct ath_rx_status *rx_stats,
bool *decrypt_error)
{
struct ath_softc *sc = (struct ath_softc *) common->priv;
bool is_mc, is_valid_tkip, strip_mic, mic_error;
struct ath_hw *ah = common->ah;
__le16 fc;
......@@ -823,7 +821,8 @@ static bool ath9k_rx_accept(struct ath_common *common,
test_bit(rx_stats->rs_keyix, common->tkip_keymap);
strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
!(rx_stats->rs_status &
(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC));
(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
ATH9K_RXERR_KEYMISS));
if (!rx_stats->rs_datalen)
return false;
......@@ -851,6 +850,8 @@ static bool ath9k_rx_accept(struct ath_common *common,
* descriptors.
*/
if (rx_stats->rs_status != 0) {
u8 status_mask;
if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
mic_error = false;
......@@ -858,7 +859,8 @@ static bool ath9k_rx_accept(struct ath_common *common,
if (rx_stats->rs_status & ATH9K_RXERR_PHY)
return false;
if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
(!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
*decrypt_error = true;
mic_error = false;
}
......@@ -868,17 +870,14 @@ static bool ath9k_rx_accept(struct ath_common *common,
* decryption and MIC failures. For monitor mode,
* we also ignore the CRC error.
*/
if (ah->is_monitoring) {
if (rx_stats->rs_status &
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
ATH9K_RXERR_CRC))
return false;
} else {
if (rx_stats->rs_status &
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
return false;
}
}
status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
ATH9K_RXERR_KEYMISS;
if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
status_mask |= ATH9K_RXERR_CRC;
if (rx_stats->rs_status & ~status_mask)
return false;
}
/*
......@@ -1973,7 +1972,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
if (!(ah->imask & ATH9K_INT_RXEOL)) {
ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
ath9k_hw_set_interrupts(ah, ah->imask);
ath9k_hw_set_interrupts(ah);
}
return 0;
......
drivers/net/wireless/ath/ath9k/reg.h
浏览文件 @ 41ebe9cd
......@@ -796,9 +796,9 @@
#define AR_SREV_VERSION_9340 0x300
#define AR_SREV_VERSION_9580 0x1C0
#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
#define AR_SREV_VERSION_9480 0x280
#define AR_SREV_REVISION_9480_10 0
#define AR_SREV_REVISION_9480_20 2
#define AR_SREV_VERSION_9462 0x280
#define AR_SREV_REVISION_9462_10 0
#define AR_SREV_REVISION_9462_20 2
#define AR_SREV_5416(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
......@@ -895,20 +895,20 @@
(AR_SREV_9285_12_OR_LATER(_ah) && \
((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
#define AR_SREV_9480(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480))
#define AR_SREV_9462(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462))
#define AR_SREV_9480_10(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \
((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_10))
#define AR_SREV_9462_10(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_10))
#define AR_SREV_9480_20(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \
((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_20))
#define AR_SREV_9462_20(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_20))
#define AR_SREV_9480_20_OR_LATER(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \
((_ah)->hw_version.macRev >= AR_SREV_REVISION_9480_20))
#define AR_SREV_9462_20_OR_LATER(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))
#define AR_SREV_9580(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
......@@ -1933,6 +1933,7 @@ enum {
#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
#define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000
#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
......
drivers/net/wireless/ath/ath9k/xmit.c
浏览文件 @ 41ebe9cd
......@@ -373,7 +373,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
struct ath_frame_info *fi;
int nframes;
u8 tidno;
bool clear_filter;
bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
skb = bf->bf_mpdu;
hdr = (struct ieee80211_hdr *)skb->data;
......@@ -462,12 +462,12 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
* the un-acked sub-frames
*/
txfail = 1;
} else if (flush) {
txpending = 1;
} else if (fi->retries < ATH_MAX_SW_RETRIES) {
if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
!an->sleeping)
if (txok || !an->sleeping)
ath_tx_set_retry(sc, txq, bf->bf_mpdu);
clear_filter = true;
txpending = 1;
} else {
txfail = 1;
......@@ -521,7 +521,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
ath_tx_complete_buf(sc, bf, txq,
&bf_head,
ts, 0, 1);
ts, 0,
!flush);
break;
}
......@@ -545,11 +546,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
ieee80211_sta_set_buffered(sta, tid->tidno, true);
spin_lock_bh(&txq->axq_lock);
if (clear_filter)
tid->ac->clear_ps_filter = true;
skb_queue_splice(&bf_pending, &tid->buf_q);
if (!an->sleeping)
if (!an->sleeping) {
ath_tx_queue_tid(txq, tid);
if (ts->ts_status & ATH9K_TXERR_FILT)
tid->ac->clear_ps_filter = true;
}
spin_unlock_bh(&txq->axq_lock);
}
......@@ -564,8 +567,10 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
rcu_read_unlock();
if (needreset)
if (needreset) {
RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
}
}
static bool ath_lookup_legacy(struct ath_buf *bf)
......@@ -1255,7 +1260,6 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
{
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_tx_queue_info qi;
static const int subtype_txq_to_hwq[] = {
[WME_AC_BE] = ATH_TXQ_AC_BE,
......@@ -1305,12 +1309,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
*/
return NULL;
}
if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
ath_err(common, "qnum %u out of range, max %zu!\n",
axq_qnum, ARRAY_SIZE(sc->tx.txq));
ath9k_hw_releasetxqueue(ah, axq_qnum);
return NULL;
}
if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
struct ath_txq *txq = &sc->tx.txq[axq_qnum];
......@@ -1407,6 +1405,7 @@ static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
struct ath_tx_status ts;
memset(&ts, 0, sizeof(ts));
ts.ts_status = ATH9K_TX_FLUSH;
INIT_LIST_HEAD(&bf_head);
while (!list_empty(list)) {
......@@ -1473,7 +1472,8 @@ bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_txq *txq;
int i, npend = 0;
int i;
u32 npend = 0;
if (sc->sc_flags & SC_OP_INVALID)
return true;
......@@ -1485,11 +1485,12 @@ bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
if (!ATH_TXQ_SETUP(sc, i))
continue;
npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
npend |= BIT(i);
}
if (npend)
ath_err(common, "Failed to stop TX DMA!\n");
ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
if (!ATH_TXQ_SETUP(sc, i))
......@@ -2211,6 +2212,7 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
if (needreset) {
ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
"tx hung, resetting the chip\n");
RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
}
......
drivers/net/wireless/ath/carl9170/main.c
浏览文件 @ 41ebe9cd
......@@ -1896,7 +1896,6 @@ static int carl9170_parse_eeprom(struct ar9170 *ar)
ar->hw->channel_change_time = 80 * 1000;
regulatory->current_rd = le16_to_cpu(ar->eeprom.reg_domain[0]);
regulatory->current_rd_ext = le16_to_cpu(ar->eeprom.reg_domain[1]);
/* second part of wiphy init */
SET_IEEE80211_PERM_ADDR(ar->hw, ar->eeprom.mac_address);
......
drivers/net/wireless/b43/xmit.c
浏览文件 @ 41ebe9cd
......@@ -735,16 +735,22 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
}
/* Link quality statistics */
if ((chanstat & B43_RX_CHAN_PHYTYPE) == B43_PHYTYPE_N) {
// s8 rssi = max(rxhdr->power0, rxhdr->power1);
//TODO: Find out what the rssi value is (dBm or percentage?)
// and also find out what the maximum possible value is.
// Fill status.ssi and status.signal fields.
} else {
switch (chanstat & B43_RX_CHAN_PHYTYPE) {
case B43_PHYTYPE_N:
if (rxhdr->power0 == 16 || rxhdr->power0 == 32)
status.signal = max(rxhdr->power1, rxhdr->power2);
else
status.signal = max(rxhdr->power0, rxhdr->power1);
break;
case B43_PHYTYPE_A:
case B43_PHYTYPE_B:
case B43_PHYTYPE_G:
case B43_PHYTYPE_LP:
status.signal = b43_rssi_postprocess(dev, rxhdr->jssi,
(phystat0 & B43_RX_PHYST0_OFDM),
(phystat0 & B43_RX_PHYST0_GAINCTL),
(phystat3 & B43_RX_PHYST3_TRSTATE));
break;
}
if (phystat0 & B43_RX_PHYST0_OFDM)
......
drivers/net/wireless/b43/xmit.h
浏览文件 @ 41ebe9cd
......@@ -248,7 +248,15 @@ struct b43_rxhdr_fw4 {
__s8 power1; /* PHY RX Status 1: Power 1 */
} __packed;
} __packed;
__le16 phy_status2; /* PHY RX Status 2 */
union {
/* RSSI for N-PHYs */
struct {
__s8 power2;
PAD_BYTES(1);
} __packed;
__le16 phy_status2; /* PHY RX Status 2 */
} __packed;
__le16 phy_status3; /* PHY RX Status 3 */
union {
/* Tested with 598.314, 644.1001 and 666.2 */
......
drivers/net/wireless/brcm80211/Kconfig 0 → 100644
浏览文件 @ 41ebe9cd
config BRCMUTIL
tristate
config BRCMSMAC
tristate "Broadcom IEEE802.11n PCIe SoftMAC WLAN driver"
depends on PCI
depends on MAC80211
depends on BCMA=n
select BRCMUTIL
select FW_LOADER
select CRC_CCITT
select CRC8
select CORDIC
---help---
This module adds support for PCIe wireless adapters based on Broadcom
IEEE802.11n SoftMAC chipsets. If you choose to build a module, it'll
be called brcmsmac.ko.
config BRCMFMAC
tristate "Broadcom IEEE802.11n embedded FullMAC WLAN driver"
depends on MMC
depends on CFG80211
select BRCMUTIL
select FW_LOADER
---help---
This module adds support for embedded wireless adapters based on
Broadcom IEEE802.11n FullMAC chipsets. This driver uses the kernel's
wireless extensions subsystem. If you choose to build a module,
it'll be called brcmfmac.ko.
config BRCMDBG
bool "Broadcom driver debug functions"
depends on BRCMSMAC || BRCMFMAC
---help---
Selecting this enables additional code for debug purposes.
drivers/net/wireless/brcm80211/Makefile 0 → 100644
浏览文件 @ 41ebe9cd
#
# Makefile fragment for Broadcom 802.11n Networking Device Driver
#
# Copyright (c) 2010 Broadcom Corporation
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# common flags
subdir-ccflags-$(CONFIG_BRCMDBG) += -DBCMDBG
obj-$(CONFIG_BRCMUTIL) += brcmutil/
obj-$(CONFIG_BRCMFMAC) += brcmfmac/
obj-$(CONFIG_BRCMSMAC) += brcmsmac/
drivers/net/wireless/brcm80211/brcmfmac/Makefile 0 → 100644
浏览文件 @ 41ebe9cd
#
# Makefile fragment for Broadcom 802.11n Networking Device Driver
#
# Copyright (c) 2010 Broadcom Corporation
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
ccflags-y += \
-Idrivers/net/wireless/brcm80211/brcmfmac \
-Idrivers/net/wireless/brcm80211/include
DHDOFILES = \
wl_cfg80211.o \
dhd_cdc.o \
dhd_common.o \
dhd_sdio.o \
dhd_linux.o \
bcmsdh.o \
bcmsdh_sdmmc.o
obj-$(CONFIG_BRCMFMAC) += brcmfmac.o
brcmfmac-objs += $(DHDOFILES)
ccflags-y += -D__CHECK_ENDIAN__
drivers/net/wireless/brcm80211/brcmfmac/bcmchip.h 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2011 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmchip_h_
#define _bcmchip_h_
/* bcm4329 */
/* SDIO device core, ID 0x829 */
#define BCM4329_CORE_BUS_BASE 0x18011000
/* internal memory core, ID 0x80e */
#define BCM4329_CORE_SOCRAM_BASE 0x18003000
/* ARM Cortex M3 core, ID 0x82a */
#define BCM4329_CORE_ARM_BASE 0x18002000
#define BCM4329_RAMSIZE 0x48000
/* firmware name */
#define BCM4329_FW_NAME "brcm/bcm4329-fullmac-4.bin"
#define BCM4329_NV_NAME "brcm/bcm4329-fullmac-4.txt"
#endif /* _bcmchip_h_ */
drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/* ****************** SDIO CARD Interface Functions **************************/
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/sched.h>
#include <linux/completion.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <soc.h>
#include "dhd.h"
#include "dhd_bus.h"
#include "dhd_dbg.h"
#include "sdio_host.h"
#define SDIOH_API_ACCESS_RETRY_LIMIT 2
static void brcmf_sdioh_irqhandler(struct sdio_func *func)
{
struct brcmf_sdio_dev *sdiodev = dev_get_drvdata(&func->card->dev);
brcmf_dbg(TRACE, "***IRQHandler\n");
sdio_release_host(func);
brcmf_sdbrcm_isr(sdiodev->bus);
sdio_claim_host(func);
}
int brcmf_sdcard_intr_reg(struct brcmf_sdio_dev *sdiodev)
{
brcmf_dbg(TRACE, "Entering\n");
sdio_claim_host(sdiodev->func[1]);
sdio_claim_irq(sdiodev->func[1], brcmf_sdioh_irqhandler);
sdio_release_host(sdiodev->func[1]);
return 0;
}
int brcmf_sdcard_intr_dereg(struct brcmf_sdio_dev *sdiodev)
{
brcmf_dbg(TRACE, "Entering\n");
sdio_claim_host(sdiodev->func[1]);
sdio_release_irq(sdiodev->func[1]);
sdio_release_host(sdiodev->func[1]);
return 0;
}
u8 brcmf_sdcard_cfg_read(struct brcmf_sdio_dev *sdiodev, uint fnc_num, u32 addr,
int *err)
{
int status;
s32 retry = 0;
u8 data = 0;
do {
if (retry) /* wait for 1 ms till bus get settled down */
udelay(1000);
status = brcmf_sdioh_request_byte(sdiodev, SDIOH_READ, fnc_num,
addr, (u8 *) &data);
} while (status != 0
&& (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
if (err)
*err = status;
brcmf_dbg(INFO, "fun = %d, addr = 0x%x, u8data = 0x%x\n",
fnc_num, addr, data);
return data;
}
void
brcmf_sdcard_cfg_write(struct brcmf_sdio_dev *sdiodev, uint fnc_num, u32 addr,
u8 data, int *err)
{
int status;
s32 retry = 0;
do {
if (retry) /* wait for 1 ms till bus get settled down */
udelay(1000);
status = brcmf_sdioh_request_byte(sdiodev, SDIOH_WRITE, fnc_num,
addr, (u8 *) &data);
} while (status != 0
&& (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
if (err)
*err = status;
brcmf_dbg(INFO, "fun = %d, addr = 0x%x, u8data = 0x%x\n",
fnc_num, addr, data);
}
int
brcmf_sdcard_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev, u32 address)
{
int err = 0;
brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
(address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
if (!err)
brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
SBSDIO_FUNC1_SBADDRMID,
(address >> 16) & SBSDIO_SBADDRMID_MASK,
&err);
if (!err)
brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
SBSDIO_FUNC1_SBADDRHIGH,
(address >> 24) & SBSDIO_SBADDRHIGH_MASK,
&err);
return err;
}
u32 brcmf_sdcard_reg_read(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size)
{
int status;
u32 word = 0;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
brcmf_dbg(INFO, "fun = 1, addr = 0x%x\n", addr);
if (bar0 != sdiodev->sbwad) {
if (brcmf_sdcard_set_sbaddr_window(sdiodev, bar0))
return 0xFFFFFFFF;
sdiodev->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
if (size == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status = brcmf_sdioh_request_word(sdiodev, SDIOH_READ, SDIO_FUNC_1,
addr, &word, size);
sdiodev->regfail = (status != 0);
brcmf_dbg(INFO, "u32data = 0x%x\n", word);
/* if ok, return appropriately masked word */
if (status == 0) {
switch (size) {
case sizeof(u8):
return word & 0xff;
case sizeof(u16):
return word & 0xffff;
case sizeof(u32):
return word;
default:
sdiodev->regfail = true;
}
}
/* otherwise, bad sdio access or invalid size */
brcmf_dbg(ERROR, "error reading addr 0x%04x size %d\n", addr, size);
return 0xFFFFFFFF;
}
u32 brcmf_sdcard_reg_write(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size,
u32 data)
{
int status;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
int err = 0;
brcmf_dbg(INFO, "fun = 1, addr = 0x%x, uint%ddata = 0x%x\n",
addr, size * 8, data);
if (bar0 != sdiodev->sbwad) {
err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
if (err)
return err;
sdiodev->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
if (size == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status =
brcmf_sdioh_request_word(sdiodev, SDIOH_WRITE, SDIO_FUNC_1,
addr, &data, size);
sdiodev->regfail = (status != 0);
if (status == 0)
return 0;
brcmf_dbg(ERROR, "error writing 0x%08x to addr 0x%04x size %d\n",
data, addr, size);
return 0xFFFFFFFF;
}
bool brcmf_sdcard_regfail(struct brcmf_sdio_dev *sdiodev)
{
return sdiodev->regfail;
}
int
brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
uint flags,
u8 *buf, uint nbytes, struct sk_buff *pkt)
{
int status;
uint incr_fix;
uint width;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
int err = 0;
brcmf_dbg(INFO, "fun = %d, addr = 0x%x, size = %d\n", fn, addr, nbytes);
/* Async not implemented yet */
if (flags & SDIO_REQ_ASYNC)
return -ENOTSUPP;
if (bar0 != sdiodev->sbwad) {
err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
if (err)
return err;
sdiodev->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
if (width == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status = brcmf_sdioh_request_buffer(sdiodev, incr_fix, SDIOH_READ,
fn, addr, width, nbytes, buf, pkt);
return status;
}
int
brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
uint flags, u8 *buf, uint nbytes, struct sk_buff *pkt)
{
uint incr_fix;
uint width;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
int err = 0;
brcmf_dbg(INFO, "fun = %d, addr = 0x%x, size = %d\n", fn, addr, nbytes);
/* Async not implemented yet */
if (flags & SDIO_REQ_ASYNC)
return -ENOTSUPP;
if (bar0 != sdiodev->sbwad) {
err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
if (err)
return err;
sdiodev->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
if (width == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
return brcmf_sdioh_request_buffer(sdiodev, incr_fix, SDIOH_WRITE, fn,
addr, width, nbytes, buf, pkt);
}
int brcmf_sdcard_rwdata(struct brcmf_sdio_dev *sdiodev, uint rw, u32 addr,
u8 *buf, uint nbytes)
{
addr &= SBSDIO_SB_OFT_ADDR_MASK;
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
return brcmf_sdioh_request_buffer(sdiodev, SDIOH_DATA_INC,
(rw ? SDIOH_WRITE : SDIOH_READ), SDIO_FUNC_1,
addr, 4, nbytes, buf, NULL);
}
int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn)
{
char t_func = (char)fn;
brcmf_dbg(TRACE, "Enter\n");
/* issue abort cmd52 command through F0 */
brcmf_sdioh_request_byte(sdiodev, SDIOH_WRITE, SDIO_FUNC_0,
SDIO_CCCR_ABORT, &t_func);
brcmf_dbg(TRACE, "Exit\n");
return 0;
}
int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
{
u32 regs = 0;
int ret = 0;
ret = brcmf_sdioh_attach(sdiodev);
if (ret)
goto out;
regs = SI_ENUM_BASE;
/* Report the BAR, to fix if needed */
sdiodev->sbwad = SI_ENUM_BASE;
/* try to attach to the target device */
sdiodev->bus = brcmf_sdbrcm_probe(0, 0, 0, 0, regs, sdiodev);
if (!sdiodev->bus) {
brcmf_dbg(ERROR, "device attach failed\n");
ret = -ENODEV;
goto out;
}
out:
if (ret)
brcmf_sdio_remove(sdiodev);
return ret;
}
EXPORT_SYMBOL(brcmf_sdio_probe);
int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev)
{
if (sdiodev->bus) {
brcmf_sdbrcm_disconnect(sdiodev->bus);
sdiodev->bus = NULL;
}
brcmf_sdioh_detach(sdiodev);
sdiodev->sbwad = 0;
return 0;
}
EXPORT_SYMBOL(brcmf_sdio_remove);
void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev, bool enable)
{
if (enable)
brcmf_sdbrcm_wd_timer(sdiodev->bus, BRCMF_WD_POLL_MS);
else
brcmf_sdbrcm_wd_timer(sdiodev->bus, 0);
}
drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/core.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/card.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/sched.h> /* request_irq() */
#include <linux/module.h>
#include <net/cfg80211.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include "sdio_host.h"
#include "dhd.h"
#include "dhd_dbg.h"
#include "wl_cfg80211.h"
#define SDIO_VENDOR_ID_BROADCOM 0x02d0
#define DMA_ALIGN_MASK 0x03
#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
#define SDIO_FUNC1_BLOCKSIZE 64
#define SDIO_FUNC2_BLOCKSIZE 512
/* devices we support, null terminated */
static const struct sdio_device_id brcmf_sdmmc_ids[] = {
{SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)},
{ /* end: all zeroes */ },
};
MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids);
static bool
brcmf_pm_resume_error(struct brcmf_sdio_dev *sdiodev)
{
bool is_err = false;
#ifdef CONFIG_PM_SLEEP
is_err = atomic_read(&sdiodev->suspend);
#endif
return is_err;
}
static void
brcmf_pm_resume_wait(struct brcmf_sdio_dev *sdiodev, wait_queue_head_t *wq)
{
#ifdef CONFIG_PM_SLEEP
int retry = 0;
while (atomic_read(&sdiodev->suspend) && retry++ != 30)
wait_event_timeout(*wq, false, HZ/100);
#endif
}
static inline int brcmf_sdioh_f0_write_byte(struct brcmf_sdio_dev *sdiodev,
uint regaddr, u8 *byte)
{
struct sdio_func *sdfunc = sdiodev->func[0];
int err_ret;
/*
* Can only directly write to some F0 registers.
* Handle F2 enable/disable and Abort command
* as a special case.
*/
if (regaddr == SDIO_CCCR_IOEx) {
sdfunc = sdiodev->func[2];
if (sdfunc) {
sdio_claim_host(sdfunc);
if (*byte & SDIO_FUNC_ENABLE_2) {
/* Enable Function 2 */
err_ret = sdio_enable_func(sdfunc);
if (err_ret)
brcmf_dbg(ERROR,
"enable F2 failed:%d\n",
err_ret);
} else {
/* Disable Function 2 */
err_ret = sdio_disable_func(sdfunc);
if (err_ret)
brcmf_dbg(ERROR,
"Disable F2 failed:%d\n",
err_ret);
}
sdio_release_host(sdfunc);
}
} else if (regaddr == SDIO_CCCR_ABORT) {
sdio_claim_host(sdfunc);
sdio_writeb(sdfunc, *byte, regaddr, &err_ret);
sdio_release_host(sdfunc);
} else if (regaddr < 0xF0) {
brcmf_dbg(ERROR, "F0 Wr:0x%02x: write disallowed\n", regaddr);
err_ret = -EPERM;
} else {
sdio_claim_host(sdfunc);
sdio_f0_writeb(sdfunc, *byte, regaddr, &err_ret);
sdio_release_host(sdfunc);
}
return err_ret;
}
int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw, uint func,
uint regaddr, u8 *byte)
{
int err_ret;
brcmf_dbg(INFO, "rw=%d, func=%d, addr=0x%05x\n", rw, func, regaddr);
brcmf_pm_resume_wait(sdiodev, &sdiodev->request_byte_wait);
if (brcmf_pm_resume_error(sdiodev))
return -EIO;
if (rw && func == 0) {
/* handle F0 separately */
err_ret = brcmf_sdioh_f0_write_byte(sdiodev, regaddr, byte);
} else {
sdio_claim_host(sdiodev->func[func]);
if (rw) /* CMD52 Write */
sdio_writeb(sdiodev->func[func], *byte, regaddr,
&err_ret);
else if (func == 0) {
*byte = sdio_f0_readb(sdiodev->func[func], regaddr,
&err_ret);
} else {
*byte = sdio_readb(sdiodev->func[func], regaddr,
&err_ret);
}
sdio_release_host(sdiodev->func[func]);
}
if (err_ret)
brcmf_dbg(ERROR, "Failed to %s byte F%d:@0x%05x=%02x, Err: %d\n",
rw ? "write" : "read", func, regaddr, *byte, err_ret);
return err_ret;
}
int brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
uint rw, uint func, uint addr, u32 *word,
uint nbytes)
{
int err_ret = -EIO;
if (func == 0) {
brcmf_dbg(ERROR, "Only CMD52 allowed to F0\n");
return -EINVAL;
}
brcmf_dbg(INFO, "rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
rw, func, addr, nbytes);
brcmf_pm_resume_wait(sdiodev, &sdiodev->request_word_wait);
if (brcmf_pm_resume_error(sdiodev))
return -EIO;
/* Claim host controller */
sdio_claim_host(sdiodev->func[func]);
if (rw) { /* CMD52 Write */
if (nbytes == 4)
sdio_writel(sdiodev->func[func], *word, addr,
&err_ret);
else if (nbytes == 2)
sdio_writew(sdiodev->func[func], (*word & 0xFFFF),
addr, &err_ret);
else
brcmf_dbg(ERROR, "Invalid nbytes: %d\n", nbytes);
} else { /* CMD52 Read */
if (nbytes == 4)
*word = sdio_readl(sdiodev->func[func], addr, &err_ret);
else if (nbytes == 2)
*word = sdio_readw(sdiodev->func[func], addr,
&err_ret) & 0xFFFF;
else
brcmf_dbg(ERROR, "Invalid nbytes: %d\n", nbytes);
}
/* Release host controller */
sdio_release_host(sdiodev->func[func]);
if (err_ret)
brcmf_dbg(ERROR, "Failed to %s word, Err: 0x%08x\n",
rw ? "write" : "read", err_ret);
return err_ret;
}
static int
brcmf_sdioh_request_packet(struct brcmf_sdio_dev *sdiodev, uint fix_inc,
uint write, uint func, uint addr,
struct sk_buff *pkt)
{
bool fifo = (fix_inc == SDIOH_DATA_FIX);
u32 SGCount = 0;
int err_ret = 0;
struct sk_buff *pnext;
brcmf_dbg(TRACE, "Enter\n");
brcmf_pm_resume_wait(sdiodev, &sdiodev->request_packet_wait);
if (brcmf_pm_resume_error(sdiodev))
return -EIO;
/* Claim host controller */
sdio_claim_host(sdiodev->func[func]);
for (pnext = pkt; pnext; pnext = pnext->next) {
uint pkt_len = pnext->len;
pkt_len += 3;
pkt_len &= 0xFFFFFFFC;
if ((write) && (!fifo)) {
err_ret = sdio_memcpy_toio(sdiodev->func[func], addr,
((u8 *) (pnext->data)),
pkt_len);
} else if (write) {
err_ret = sdio_memcpy_toio(sdiodev->func[func], addr,
((u8 *) (pnext->data)),
pkt_len);
} else if (fifo) {
err_ret = sdio_readsb(sdiodev->func[func],
((u8 *) (pnext->data)),
addr, pkt_len);
} else {
err_ret = sdio_memcpy_fromio(sdiodev->func[func],
((u8 *) (pnext->data)),
addr, pkt_len);
}
if (err_ret) {
brcmf_dbg(ERROR, "%s FAILED %p[%d], addr=0x%05x, pkt_len=%d, ERR=0x%08x\n",
write ? "TX" : "RX", pnext, SGCount, addr,
pkt_len, err_ret);
} else {
brcmf_dbg(TRACE, "%s xfr'd %p[%d], addr=0x%05x, len=%d\n",
write ? "TX" : "RX", pnext, SGCount, addr,
pkt_len);
}
if (!fifo)
addr += pkt_len;
SGCount++;
}
/* Release host controller */
sdio_release_host(sdiodev->func[func]);
brcmf_dbg(TRACE, "Exit\n");
return err_ret;
}
/*
* This function takes a buffer or packet, and fixes everything up
* so that in the end, a DMA-able packet is created.
*
* A buffer does not have an associated packet pointer,
* and may or may not be aligned.
* A packet may consist of a single packet, or a packet chain.
* If it is a packet chain, then all the packets in the chain
* must be properly aligned.
*
* If the packet data is not aligned, then there may only be
* one packet, and in this case, it is copied to a new
* aligned packet.
*
*/
int brcmf_sdioh_request_buffer(struct brcmf_sdio_dev *sdiodev,
uint fix_inc, uint write, uint func, uint addr,
uint reg_width, uint buflen_u, u8 *buffer,
struct sk_buff *pkt)
{
int Status;
struct sk_buff *mypkt = NULL;
brcmf_dbg(TRACE, "Enter\n");
brcmf_pm_resume_wait(sdiodev, &sdiodev->request_buffer_wait);
if (brcmf_pm_resume_error(sdiodev))
return -EIO;
/* Case 1: we don't have a packet. */
if (pkt == NULL) {
brcmf_dbg(DATA, "Creating new %s Packet, len=%d\n",
write ? "TX" : "RX", buflen_u);
mypkt = brcmu_pkt_buf_get_skb(buflen_u);
if (!mypkt) {
brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: len %d\n",
buflen_u);
return -EIO;
}
/* For a write, copy the buffer data into the packet. */
if (write)
memcpy(mypkt->data, buffer, buflen_u);
Status = brcmf_sdioh_request_packet(sdiodev, fix_inc, write,
func, addr, mypkt);
/* For a read, copy the packet data back to the buffer. */
if (!write)
memcpy(buffer, mypkt->data, buflen_u);
brcmu_pkt_buf_free_skb(mypkt);
} else if (((ulong) (pkt->data) & DMA_ALIGN_MASK) != 0) {
/*
* Case 2: We have a packet, but it is unaligned.
* In this case, we cannot have a chain (pkt->next == NULL)
*/
brcmf_dbg(DATA, "Creating aligned %s Packet, len=%d\n",
write ? "TX" : "RX", pkt->len);
mypkt = brcmu_pkt_buf_get_skb(pkt->len);
if (!mypkt) {
brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: len %d\n",
pkt->len);
return -EIO;
}
/* For a write, copy the buffer data into the packet. */
if (write)
memcpy(mypkt->data, pkt->data, pkt->len);
Status = brcmf_sdioh_request_packet(sdiodev, fix_inc, write,
func, addr, mypkt);
/* For a read, copy the packet data back to the buffer. */
if (!write)
memcpy(pkt->data, mypkt->data, mypkt->len);
brcmu_pkt_buf_free_skb(mypkt);
} else { /* case 3: We have a packet and
it is aligned. */
brcmf_dbg(DATA, "Aligned %s Packet, direct DMA\n",
write ? "Tx" : "Rx");
Status = brcmf_sdioh_request_packet(sdiodev, fix_inc, write,
func, addr, pkt);
}
return Status;
}
/* Read client card reg */
static int
brcmf_sdioh_card_regread(struct brcmf_sdio_dev *sdiodev, int func, u32 regaddr,
int regsize, u32 *data)
{
if ((func == 0) || (regsize == 1)) {
u8 temp = 0;
brcmf_sdioh_request_byte(sdiodev, SDIOH_READ, func, regaddr,
&temp);
*data = temp;
*data &= 0xff;
brcmf_dbg(DATA, "byte read data=0x%02x\n", *data);
} else {
brcmf_sdioh_request_word(sdiodev, SDIOH_READ, func, regaddr,
data, regsize);
if (regsize == 2)
*data &= 0xffff;
brcmf_dbg(DATA, "word read data=0x%08x\n", *data);
}
return SUCCESS;
}
static int brcmf_sdioh_get_cisaddr(struct brcmf_sdio_dev *sdiodev, u32 regaddr)
{
/* read 24 bits and return valid 17 bit addr */
int i;
u32 scratch, regdata;
__le32 scratch_le;
u8 *ptr = (u8 *)&scratch_le;
for (i = 0; i < 3; i++) {
if ((brcmf_sdioh_card_regread(sdiodev, 0, regaddr, 1,
&regdata)) != SUCCESS)
brcmf_dbg(ERROR, "Can't read!\n");
*ptr++ = (u8) regdata;
regaddr++;
}
/* Only the lower 17-bits are valid */
scratch = le32_to_cpu(scratch_le);
scratch &= 0x0001FFFF;
return scratch;
}
static int brcmf_sdioh_enablefuncs(struct brcmf_sdio_dev *sdiodev)
{
int err_ret;
u32 fbraddr;
u8 func;
brcmf_dbg(TRACE, "\n");
/* Get the Card's common CIS address */
sdiodev->func_cis_ptr[0] = brcmf_sdioh_get_cisaddr(sdiodev,
SDIO_CCCR_CIS);
brcmf_dbg(INFO, "Card's Common CIS Ptr = 0x%x\n",
sdiodev->func_cis_ptr[0]);
/* Get the Card's function CIS (for each function) */
for (fbraddr = SDIO_FBR_BASE(1), func = 1;
func <= sdiodev->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
sdiodev->func_cis_ptr[func] =
brcmf_sdioh_get_cisaddr(sdiodev, SDIO_FBR_CIS + fbraddr);
brcmf_dbg(INFO, "Function %d CIS Ptr = 0x%x\n",
func, sdiodev->func_cis_ptr[func]);
}
/* Enable Function 1 */
sdio_claim_host(sdiodev->func[1]);
err_ret = sdio_enable_func(sdiodev->func[1]);
sdio_release_host(sdiodev->func[1]);
if (err_ret)
brcmf_dbg(ERROR, "Failed to enable F1 Err: 0x%08x\n", err_ret);
return false;
}
/*
* Public entry points & extern's
*/
int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev)
{
int err_ret = 0;
brcmf_dbg(TRACE, "\n");
sdiodev->num_funcs = 2;
sdio_claim_host(sdiodev->func[1]);
err_ret = sdio_set_block_size(sdiodev->func[1], SDIO_FUNC1_BLOCKSIZE);
sdio_release_host(sdiodev->func[1]);
if (err_ret) {
brcmf_dbg(ERROR, "Failed to set F1 blocksize\n");
goto out;
}
sdio_claim_host(sdiodev->func[2]);
err_ret = sdio_set_block_size(sdiodev->func[2], SDIO_FUNC2_BLOCKSIZE);
sdio_release_host(sdiodev->func[2]);
if (err_ret) {
brcmf_dbg(ERROR, "Failed to set F2 blocksize\n");
goto out;
}
brcmf_sdioh_enablefuncs(sdiodev);
out:
brcmf_dbg(TRACE, "Done\n");
return err_ret;
}
void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev)
{
brcmf_dbg(TRACE, "\n");
/* Disable Function 2 */
sdio_claim_host(sdiodev->func[2]);
sdio_disable_func(sdiodev->func[2]);
sdio_release_host(sdiodev->func[2]);
/* Disable Function 1 */
sdio_claim_host(sdiodev->func[1]);
sdio_disable_func(sdiodev->func[1]);
sdio_release_host(sdiodev->func[1]);
}
static int brcmf_ops_sdio_probe(struct sdio_func *func,
const struct sdio_device_id *id)
{
int ret = 0;
struct brcmf_sdio_dev *sdiodev;
brcmf_dbg(TRACE, "Enter\n");
brcmf_dbg(TRACE, "func->class=%x\n", func->class);
brcmf_dbg(TRACE, "sdio_vendor: 0x%04x\n", func->vendor);
brcmf_dbg(TRACE, "sdio_device: 0x%04x\n", func->device);
brcmf_dbg(TRACE, "Function#: 0x%04x\n", func->num);
if (func->num == 1) {
if (dev_get_drvdata(&func->card->dev)) {
brcmf_dbg(ERROR, "card private drvdata occupied\n");
return -ENXIO;
}
sdiodev = kzalloc(sizeof(struct brcmf_sdio_dev), GFP_KERNEL);
if (!sdiodev)
return -ENOMEM;
sdiodev->func[0] = func->card->sdio_func[0];
sdiodev->func[1] = func;
dev_set_drvdata(&func->card->dev, sdiodev);
atomic_set(&sdiodev->suspend, false);
init_waitqueue_head(&sdiodev->request_byte_wait);
init_waitqueue_head(&sdiodev->request_word_wait);
init_waitqueue_head(&sdiodev->request_packet_wait);
init_waitqueue_head(&sdiodev->request_buffer_wait);
}
if (func->num == 2) {
sdiodev = dev_get_drvdata(&func->card->dev);
if ((!sdiodev) || (sdiodev->func[1]->card != func->card))
return -ENODEV;
sdiodev->func[2] = func;
brcmf_dbg(TRACE, "F2 found, calling brcmf_sdio_probe...\n");
ret = brcmf_sdio_probe(sdiodev);
}
return ret;
}
static void brcmf_ops_sdio_remove(struct sdio_func *func)
{
struct brcmf_sdio_dev *sdiodev;
brcmf_dbg(TRACE, "Enter\n");
brcmf_dbg(INFO, "func->class=%x\n", func->class);
brcmf_dbg(INFO, "sdio_vendor: 0x%04x\n", func->vendor);
brcmf_dbg(INFO, "sdio_device: 0x%04x\n", func->device);
brcmf_dbg(INFO, "Function#: 0x%04x\n", func->num);
if (func->num == 2) {
sdiodev = dev_get_drvdata(&func->card->dev);
brcmf_dbg(TRACE, "F2 found, calling brcmf_sdio_remove...\n");
brcmf_sdio_remove(sdiodev);
dev_set_drvdata(&func->card->dev, NULL);
kfree(sdiodev);
}
}
#ifdef CONFIG_PM_SLEEP
static int brcmf_sdio_suspend(struct device *dev)
{
mmc_pm_flag_t sdio_flags;
struct brcmf_sdio_dev *sdiodev;
struct sdio_func *func = dev_to_sdio_func(dev);
int ret = 0;
brcmf_dbg(TRACE, "\n");
sdiodev = dev_get_drvdata(&func->card->dev);
atomic_set(&sdiodev->suspend, true);
sdio_flags = sdio_get_host_pm_caps(sdiodev->func[1]);
if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
brcmf_dbg(ERROR, "Host can't keep power while suspended\n");
return -EINVAL;
}
ret = sdio_set_host_pm_flags(sdiodev->func[1], MMC_PM_KEEP_POWER);
if (ret) {
brcmf_dbg(ERROR, "Failed to set pm_flags\n");
return ret;
}
brcmf_sdio_wdtmr_enable(sdiodev, false);
return ret;
}
static int brcmf_sdio_resume(struct device *dev)
{
struct brcmf_sdio_dev *sdiodev;
struct sdio_func *func = dev_to_sdio_func(dev);
sdiodev = dev_get_drvdata(&func->card->dev);
brcmf_sdio_wdtmr_enable(sdiodev, true);
atomic_set(&sdiodev->suspend, false);
return 0;
}
static const struct dev_pm_ops brcmf_sdio_pm_ops = {
.suspend = brcmf_sdio_suspend,
.resume = brcmf_sdio_resume,
};
#endif /* CONFIG_PM_SLEEP */
static struct sdio_driver brcmf_sdmmc_driver = {
.probe = brcmf_ops_sdio_probe,
.remove = brcmf_ops_sdio_remove,
.name = "brcmfmac",
.id_table = brcmf_sdmmc_ids,
#ifdef CONFIG_PM_SLEEP
.drv = {
.pm = &brcmf_sdio_pm_ops,
},
#endif /* CONFIG_PM_SLEEP */
};
/* bus register interface */
int brcmf_bus_register(void)
{
brcmf_dbg(TRACE, "Enter\n");
return sdio_register_driver(&brcmf_sdmmc_driver);
}
void brcmf_bus_unregister(void)
{
brcmf_dbg(TRACE, "Enter\n");
sdio_unregister_driver(&brcmf_sdmmc_driver);
}
drivers/net/wireless/brcm80211/brcmfmac/dhd.h 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BRCMF_BUS_H_
#define _BRCMF_BUS_H_
/* Packet alignment for most efficient SDIO (can change based on platform) */
#define BRCMF_SDALIGN (1 << 6)
/* watchdog polling interval in ms */
#define BRCMF_WD_POLL_MS 10
/*
* Exported from brcmf bus module (brcmf_usb, brcmf_sdio)
*/
/* Indicate (dis)interest in finding dongles. */
extern int brcmf_bus_register(void);
extern void brcmf_bus_unregister(void);
/* obtain linux device object providing bus function */
extern struct device *brcmf_bus_get_device(struct brcmf_bus *bus);
/* Stop bus module: clear pending frames, disable data flow */
extern void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus);
/* Initialize bus module: prepare for communication w/dongle */
extern int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr);
/* Send a data frame to the dongle. Callee disposes of txp. */
extern int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *txp);
/* Send/receive a control message to/from the dongle.
* Expects caller to enforce a single outstanding transaction.
*/
extern int
brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen);
extern int
brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen);
extern void brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick);
#endif /* _BRCMF_BUS_H_ */
drivers/net/wireless/brcm80211/brcmfmac/dhd_cdc.c 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BRCMF_DBG_H_
#define _BRCMF_DBG_H_
#if defined(BCMDBG)
#define brcmf_dbg(level, fmt, ...) \
do { \
if (BRCMF_ERROR_VAL == BRCMF_##level##_VAL) { \
if (brcmf_msg_level & BRCMF_##level##_VAL) { \
if (net_ratelimit()) \
printk(KERN_DEBUG "%s: " fmt, \
__func__, ##__VA_ARGS__); \
} \
} else { \
if (brcmf_msg_level & BRCMF_##level##_VAL) { \
printk(KERN_DEBUG "%s: " fmt, \
__func__, ##__VA_ARGS__); \
} \
} \
} while (0)
#define BRCMF_DATA_ON() (brcmf_msg_level & BRCMF_DATA_VAL)
#define BRCMF_CTL_ON() (brcmf_msg_level & BRCMF_CTL_VAL)
#define BRCMF_HDRS_ON() (brcmf_msg_level & BRCMF_HDRS_VAL)
#define BRCMF_BYTES_ON() (brcmf_msg_level & BRCMF_BYTES_VAL)
#define BRCMF_GLOM_ON() (brcmf_msg_level & BRCMF_GLOM_VAL)
#else /* (defined BCMDBG) || (defined BCMDBG) */
#define brcmf_dbg(level, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
#define BRCMF_DATA_ON() 0
#define BRCMF_CTL_ON() 0
#define BRCMF_HDRS_ON() 0
#define BRCMF_BYTES_ON() 0
#define BRCMF_GLOM_ON() 0
#endif /* defined(BCMDBG) */
extern int brcmf_msg_level;
#endif /* _BRCMF_DBG_H_ */
drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmfmac/dhd_proto.h 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BRCMF_PROTO_H_
#define _BRCMF_PROTO_H_
/*
* Exported from the brcmf protocol module (brcmf_cdc)
*/
/* Linkage, sets prot link and updates hdrlen in pub */
extern int brcmf_proto_attach(struct brcmf_pub *drvr);
/* Unlink, frees allocated protocol memory (including brcmf_proto) */
extern void brcmf_proto_detach(struct brcmf_pub *drvr);
/* Initialize protocol: sync w/dongle state.
* Sets dongle media info (iswl, drv_version, mac address).
*/
extern int brcmf_proto_init(struct brcmf_pub *drvr);
/* Stop protocol: sync w/dongle state. */
extern void brcmf_proto_stop(struct brcmf_pub *drvr);
/* Add any protocol-specific data header.
* Caller must reserve prot_hdrlen prepend space.
*/
extern void brcmf_proto_hdrpush(struct brcmf_pub *, int ifidx,
struct sk_buff *txp);
/* Remove any protocol-specific data header. */
extern int brcmf_proto_hdrpull(struct brcmf_pub *, int *ifidx,
struct sk_buff *rxp);
/* Use protocol to issue command to dongle */
extern int brcmf_proto_dcmd(struct brcmf_pub *drvr, int ifidx,
struct brcmf_dcmd *dcmd, int len);
/* Update local copy of dongle statistics */
extern void brcmf_proto_dstats(struct brcmf_pub *drvr);
extern int brcmf_c_preinit_dcmds(struct brcmf_pub *drvr);
extern int brcmf_proto_cdc_set_dcmd(struct brcmf_pub *drvr, int ifidx,
uint cmd, void *buf, uint len);
#endif /* _BRCMF_PROTO_H_ */
drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BRCM_SDH_H_
#define _BRCM_SDH_H_
#include <linux/skbuff.h>
#define SDIO_FUNC_0 0
#define SDIO_FUNC_1 1
#define SDIO_FUNC_2 2
#define SDIOD_FBR_SIZE 0x100
/* io_en */
#define SDIO_FUNC_ENABLE_1 0x02
#define SDIO_FUNC_ENABLE_2 0x04
/* io_rdys */
#define SDIO_FUNC_READY_1 0x02
#define SDIO_FUNC_READY_2 0x04
/* intr_status */
#define INTR_STATUS_FUNC1 0x2
#define INTR_STATUS_FUNC2 0x4
/* Maximum number of I/O funcs */
#define SDIOD_MAX_IOFUNCS 7
/* as of sdiod rev 0, supports 3 functions */
#define SBSDIO_NUM_FUNCTION 3
/* function 1 miscellaneous registers */
/* sprom command and status */
#define SBSDIO_SPROM_CS 0x10000
/* sprom info register */
#define SBSDIO_SPROM_INFO 0x10001
/* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_LOW 0x10002
/* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_HIGH 0x10005
/* xtal_pu (gpio) output */
#define SBSDIO_CHIP_CTRL_DATA 0x10006
/* xtal_pu (gpio) enable */
#define SBSDIO_CHIP_CTRL_EN 0x10007
/* rev < 7, watermark for sdio device */
#define SBSDIO_WATERMARK 0x10008
/* control busy signal generation */
#define SBSDIO_DEVICE_CTL 0x10009
/* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
/* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRMID 0x1000B
/* SB Address Window High (b31:b24) */
#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
/* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
/* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
/* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
/* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
/* Write Frame Byte Count High */
#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
/* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
/* Read Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
/* function 1 OCP space */
/* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
/* with b15, maps to 32-bit SB access */
#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
/* Address bits from SBADDR regs */
#define SBSDIO_SBWINDOW_MASK 0xffff8000
#define SDIOH_READ 0 /* Read request */
#define SDIOH_WRITE 1 /* Write request */
#define SDIOH_DATA_FIX 0 /* Fixed addressing */
#define SDIOH_DATA_INC 1 /* Incremental addressing */
/* internal return code */
#define SUCCESS 0
#define ERROR 1
struct brcmf_sdreg {
int func;
int offset;
int value;
};
struct brcmf_sdio_dev {
struct sdio_func *func[SDIO_MAX_FUNCS];
u8 num_funcs; /* Supported funcs on client */
u32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
u32 sbwad; /* Save backplane window address */
bool regfail; /* status of last reg_r/w call */
void *bus;
atomic_t suspend; /* suspend flag */
wait_queue_head_t request_byte_wait;
wait_queue_head_t request_word_wait;
wait_queue_head_t request_packet_wait;
wait_queue_head_t request_buffer_wait;
};
/* Register/deregister device interrupt handler. */
extern int
brcmf_sdcard_intr_reg(struct brcmf_sdio_dev *sdiodev);
extern int brcmf_sdcard_intr_dereg(struct brcmf_sdio_dev *sdiodev);
/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
* fn: function number
* addr: unmodified SDIO-space address
* data: data byte to write
* err: pointer to error code (or NULL)
*/
extern u8 brcmf_sdcard_cfg_read(struct brcmf_sdio_dev *sdiodev, uint func,
u32 addr, int *err);
extern void brcmf_sdcard_cfg_write(struct brcmf_sdio_dev *sdiodev, uint func,
u32 addr, u8 data, int *err);
/* Synchronous access to device (client) core registers via CMD53 to F1.
* addr: backplane address (i.e. >= regsva from attach)
* size: register width in bytes (2 or 4)
* data: data for register write
*/
extern u32
brcmf_sdcard_reg_read(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size);
extern u32
brcmf_sdcard_reg_write(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size,
u32 data);
/* Indicate if last reg read/write failed */
extern bool brcmf_sdcard_regfail(struct brcmf_sdio_dev *sdiodev);
/* Buffer transfer to/from device (client) core via cmd53.
* fn: function number
* addr: backplane address (i.e. >= regsva from attach)
* flags: backplane width, address increment, sync/async
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* pkt: pointer to packet associated with buf (if any)
* complete: callback function for command completion (async only)
* handle: handle for completion callback (first arg in callback)
* Returns 0 or error code.
* NOTE: Async operation is not currently supported.
*/
extern int
brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
uint flags, u8 *buf, uint nbytes, struct sk_buff *pkt);
extern int
brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
uint flags, u8 *buf, uint nbytes, struct sk_buff *pkt);
/* Flags bits */
/* Four-byte target (backplane) width (vs. two-byte) */
#define SDIO_REQ_4BYTE 0x1
/* Fixed address (FIFO) (vs. incrementing address) */
#define SDIO_REQ_FIXED 0x2
/* Async request (vs. sync request) */
#define SDIO_REQ_ASYNC 0x4
/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
* rw: read or write (0/1)
* addr: direct SDIO address
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* Returns 0 or error code.
*/
extern int brcmf_sdcard_rwdata(struct brcmf_sdio_dev *sdiodev, uint rw,
u32 addr, u8 *buf, uint nbytes);
/* Issue an abort to the specified function */
extern int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
/* platform specific/high level functions */
extern int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
extern int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev);
extern int brcmf_sdcard_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev,
u32 address);
/* attach, return handler on success, NULL if failed.
* The handler shall be provided by all subsequent calls. No local cache
* cfghdl points to the starting address of pci device mapped memory
*/
extern int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev);
extern void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev);
/* read or write one byte using cmd52 */
extern int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw,
uint fnc, uint addr, u8 *byte);
/* read or write 2/4 bytes using cmd53 */
extern int
brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
uint rw, uint fnc, uint addr,
u32 *word, uint nbyte);
/* read or write any buffer using cmd53 */
extern int
brcmf_sdioh_request_buffer(struct brcmf_sdio_dev *sdiodev,
uint fix_inc, uint rw, uint fnc_num,
u32 addr, uint regwidth,
u32 buflen, u8 *buffer, struct sk_buff *pkt);
/* Watchdog timer interface for pm ops */
extern void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev,
bool enable);
extern void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
u32 regsva, struct brcmf_sdio_dev *sdiodev);
extern void brcmf_sdbrcm_disconnect(void *ptr);
extern void brcmf_sdbrcm_isr(void *arg);
#endif /* _BRCM_SDH_H_ */
drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmsmac/Makefile 0 → 100644
浏览文件 @ 41ebe9cd
#
# Makefile fragment for Broadcom 802.11n Networking Device Driver
#
# Copyright (c) 2010 Broadcom Corporation
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
ccflags-y := \
-D__CHECK_ENDIAN__ \
-Idrivers/net/wireless/brcm80211/brcmsmac \
-Idrivers/net/wireless/brcm80211/brcmsmac/phy \
-Idrivers/net/wireless/brcm80211/include
BRCMSMAC_OFILES := \
mac80211_if.o \
ucode_loader.o \
ampdu.o \
antsel.o \
channel.o \
main.o \
phy_shim.o \
pmu.o \
rate.o \
stf.o \
aiutils.o \
phy/phy_cmn.o \
phy/phy_lcn.o \
phy/phy_n.o \
phy/phytbl_lcn.o \
phy/phytbl_n.o \
phy/phy_qmath.o \
otp.o \
srom.o \
dma.o \
nicpci.o \
brcms_trace_events.o
MODULEPFX := brcmsmac
obj-$(CONFIG_BRCMSMAC) += $(MODULEPFX).o
$(MODULEPFX)-objs = $(BRCMSMAC_OFILES)
drivers/net/wireless/brcm80211/brcmsmac/aiutils.c 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmsmac/aiutils.h 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmsmac/ampdu.c 0 → 100644
浏览文件 @ 41ebe9cd
此差异已折叠。
drivers/net/wireless/brcm80211/brcmsmac/ampdu.h 0 → 100644
浏览文件 @ 41ebe9cd
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BRCM_AMPDU_H_
#define _BRCM_AMPDU_H_
extern struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc);
extern void brcms_c_ampdu_detach(struct ampdu_info *ampdu);
extern int brcms_c_sendampdu(struct ampdu_info *ampdu,
struct brcms_txq_info *qi,
struct sk_buff **aggp, int prec);
extern void brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
struct sk_buff *p, struct tx_status *txs);
extern void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc);
extern void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu);
#endif /* _BRCM_AMPDU_H_ */
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