perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints

mainline inclusion
from mainline-v5.16-rc1
commit 4034fb20
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO

Intel-SIG: commit 4034fb20 perf/x86/intel/uncore: Fix Intel SPR
M3UPI event constraints
This commit is backported as a fix to SPR PMU uncore support.

-------------------------------------

SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.

Fixes: 2a8e51ea ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: NKan Liang <kan.liang@linux.intel.com>
Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.comSigned-off-by: NYunying Sun <yunying.sun@intel.com>

arch/x86/events/intel/uncore_snbep.c

@@ -5609,6 +5609,7 @@ static struct intel_uncore_type spr_uncore_upi = {
 static struct intel_uncore_type spr_uncore_m3upi = {
 	SPR_UNCORE_PCI_COMMON_FORMAT(),
 	.name			= "m3upi",
+	.constraints		= icx_uncore_m3upi_constraints,
 };
 
 static struct intel_uncore_type spr_uncore_mdf = {