提交 3c68157f 编写于 作者: O Oded Gabbay

habanalabs/gaudi: add support for NIC QMANs

Initialize the QMANs that are responsible to submit doorbells to the NIC
engines. Add support for stopping and disabling them, and reset them as
part of the hard-reset procedure of GAUDI. This will allow the user to
submit work to the NICs.

Add support for receiving events on QMAN errors from the firmware.

However, the nic_ports_mask is still initialized to 0. That means this code
won't initialize the QMANs just yet. That will be in a later patch.
Signed-off-by: NOmer Shpigelman <oshpigelman@habana.ai>
Reviewed-by: NOded Gabbay <ogabbay@kernel.org>
Signed-off-by: NOded Gabbay <ogabbay@kernel.org>
上级 11dcb8c7
...@@ -1633,8 +1633,6 @@ struct hl_mmu_funcs { ...@@ -1633,8 +1633,6 @@ struct hl_mmu_funcs {
* @pmmu_huge_range: is a different virtual addresses range used for PMMU with * @pmmu_huge_range: is a different virtual addresses range used for PMMU with
* huge pages. * huge pages.
* @init_done: is the initialization of the device done. * @init_done: is the initialization of the device done.
* @mmu_enable: is MMU enabled.
* @mmu_huge_page_opt: is MMU huge pages optimization enabled.
* @device_cpu_disabled: is the device CPU disabled (due to timeouts) * @device_cpu_disabled: is the device CPU disabled (due to timeouts)
* @dma_mask: the dma mask that was set for this device * @dma_mask: the dma mask that was set for this device
* @in_debug: is device under debug. This, together with fpriv_list, enforces * @in_debug: is device under debug. This, together with fpriv_list, enforces
...@@ -1750,6 +1748,7 @@ struct hl_device { ...@@ -1750,6 +1748,7 @@ struct hl_device {
u8 supports_cb_mapping; u8 supports_cb_mapping;
/* Parameters for bring-up */ /* Parameters for bring-up */
u64 nic_ports_mask;
u64 fw_loading; u64 fw_loading;
u8 mmu_enable; u8 mmu_enable;
u8 mmu_huge_page_opt; u8 mmu_huge_page_opt;
......
...@@ -79,6 +79,7 @@ ...@@ -79,6 +79,7 @@
#define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE) #define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE)
#define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE) #define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE)
#define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE) #define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
#define NIC_ENGINE_QMAN_OFFSET (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
#define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE) #define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
...@@ -140,6 +141,10 @@ ...@@ -140,6 +141,10 @@
#define TPC_QMAN_LENGTH 1024 #define TPC_QMAN_LENGTH 1024
#define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) #define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
#define NIC_QMAN_LENGTH 1024
#define NIC_QMAN_SIZE_IN_BYTES (NIC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
#define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START #define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
/* Virtual address space */ /* Virtual address space */
...@@ -161,6 +166,19 @@ ...@@ -161,6 +166,19 @@
#define HW_CAP_SRAM_SCRAMBLER BIT(10) #define HW_CAP_SRAM_SCRAMBLER BIT(10)
#define HW_CAP_HBM_SCRAMBLER BIT(11) #define HW_CAP_HBM_SCRAMBLER BIT(11)
#define HW_CAP_NIC0 BIT(14)
#define HW_CAP_NIC1 BIT(15)
#define HW_CAP_NIC2 BIT(16)
#define HW_CAP_NIC3 BIT(17)
#define HW_CAP_NIC4 BIT(18)
#define HW_CAP_NIC5 BIT(19)
#define HW_CAP_NIC6 BIT(20)
#define HW_CAP_NIC7 BIT(21)
#define HW_CAP_NIC8 BIT(22)
#define HW_CAP_NIC9 BIT(23)
#define HW_CAP_NIC_MASK GENMASK(23, 14)
#define HW_CAP_NIC_SHIFT 14
#define HW_CAP_TPC0 BIT(24) #define HW_CAP_TPC0 BIT(24)
#define HW_CAP_TPC1 BIT(25) #define HW_CAP_TPC1 BIT(25)
#define HW_CAP_TPC2 BIT(26) #define HW_CAP_TPC2 BIT(26)
...@@ -208,6 +226,20 @@ enum gaudi_tpc_mask { ...@@ -208,6 +226,20 @@ enum gaudi_tpc_mask {
GAUDI_TPC_MASK_ALL = 0xFF GAUDI_TPC_MASK_ALL = 0xFF
}; };
enum gaudi_nic_mask {
GAUDI_NIC_MASK_NIC0 = 0x01,
GAUDI_NIC_MASK_NIC1 = 0x02,
GAUDI_NIC_MASK_NIC2 = 0x04,
GAUDI_NIC_MASK_NIC3 = 0x08,
GAUDI_NIC_MASK_NIC4 = 0x10,
GAUDI_NIC_MASK_NIC5 = 0x20,
GAUDI_NIC_MASK_NIC6 = 0x40,
GAUDI_NIC_MASK_NIC7 = 0x80,
GAUDI_NIC_MASK_NIC8 = 0x100,
GAUDI_NIC_MASK_NIC9 = 0x200,
GAUDI_NIC_MASK_ALL = 0x3FF
};
/** /**
* struct gaudi_internal_qman_info - Internal QMAN information. * struct gaudi_internal_qman_info - Internal QMAN information.
* @pq_kernel_addr: Kernel address of the PQ memory area in the host. * @pq_kernel_addr: Kernel address of the PQ memory area in the host.
......
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