arm64: dts: ti: k3-j7200: Fix the L2 cache sets

stable inclusion
from stable-v5.10.94
commit 2dcfa3c76596cdf4c3911bc11762f1ce80716e53
bugzilla: https://gitee.com/openeuler/kernel/issues/I531X9

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=2dcfa3c76596cdf4c3911bc11762f1ce80716e53

--------------------------------

[ Upstream commit d0c82610 ]

A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed88 ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: NPeng Fan <peng.fan@nxp.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NPratyush Yadav <p.yadav@ti.com>
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.comSigned-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>

arch/arm64/boot/dts/ti/k3-j7200.dtsi

@@ -84,7 +84,7 @@
 		cache-level = <2>;
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
-		cache-sets = <2048>;
+		cache-sets = <1024>;
 		next-level-cache = <&msmc_l3>;
 	};