Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openeuler
Kernel
提交
34adb28d
K
Kernel
项目概览
openeuler
/
Kernel
1 年多 前同步成功
通知
8
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
K
Kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
提交
34adb28d
编写于
11月 22, 2014
作者:
R
Ralf Baechle
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT
Signed-off-by:
N
Ralf Baechle
<
ralf@linux-mips.org
>
上级
f9861407
变更
15
隐藏空白更改
内联
并排
Showing
15 changed file
with
40 addition
and
43 deletion
+40
-43
arch/mips/Kconfig
arch/mips/Kconfig
+6
-9
arch/mips/alchemy/common/setup.c
arch/mips/alchemy/common/setup.c
+1
-1
arch/mips/include/asm/mach-au1x00/ioremap.h
arch/mips/include/asm/mach-au1x00/ioremap.h
+1
-1
arch/mips/include/asm/page.h
arch/mips/include/asm/page.h
+1
-1
arch/mips/include/asm/pgtable-32.h
arch/mips/include/asm/pgtable-32.h
+7
-7
arch/mips/include/asm/pgtable-bits.h
arch/mips/include/asm/pgtable-bits.h
+2
-2
arch/mips/include/asm/pgtable.h
arch/mips/include/asm/pgtable.h
+4
-4
arch/mips/include/asm/types.h
arch/mips/include/asm/types.h
+1
-1
arch/mips/mm/gup.c
arch/mips/mm/gup.c
+1
-1
arch/mips/mm/init.c
arch/mips/mm/init.c
+1
-1
arch/mips/mm/tlb-r4k.c
arch/mips/mm/tlb-r4k.c
+1
-1
arch/mips/mm/tlbex.c
arch/mips/mm/tlbex.c
+9
-9
arch/mips/sibyte/common/cfe.c
arch/mips/sibyte/common/cfe.c
+2
-2
drivers/dma/txx9dmac.c
drivers/dma/txx9dmac.c
+1
-1
drivers/dma/txx9dmac.h
drivers/dma/txx9dmac.h
+2
-2
未找到文件。
arch/mips/Kconfig
浏览文件 @
34adb28d
...
...
@@ -63,7 +63,7 @@ choice
config MIPS_ALCHEMY
bool "Alchemy processor based machines"
select
64BIT_PHYS_ADDR
select
ARCH_PHYS_ADDR_T_64BIT
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
...
...
@@ -771,7 +771,7 @@ config MIKROTIK_RB532
config CAVIUM_OCTEON_SOC
bool "Cavium Networks Octeon SoC based boards"
select CEVT_R4K
select
64BIT_PHYS_ADDR
select
ARCH_PHYS_ADDR_T_64BIT
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
...
...
@@ -813,7 +813,7 @@ config NLM_XLR_BOARD
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select
64BIT_PHYS_ADDR
select
ARCH_PHYS_ADDR_T_64BIT
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select DMA_COHERENT
...
...
@@ -839,7 +839,7 @@ config NLM_XLP_BOARD
select HW_HAS_PCI
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select
64BIT_PHYS_ADDR
select
ARCH_PHYS_ADDR_T_64BIT
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
...
...
@@ -979,7 +979,7 @@ config FW_CFE
bool
config ARCH_DMA_ADDR_T_64BIT
def_bool (HIGHMEM &&
64BIT_PHYS_ADDR
) || 64BIT
def_bool (HIGHMEM &&
ARCH_PHYS_ADDR_T_64BIT
) || 64BIT
config DMA_MAYBE_COHERENT
select DMA_NONCOHERENT
...
...
@@ -2124,11 +2124,8 @@ config SB1_PASS_2_1_WORKAROUNDS
default y
config 64BIT_PHYS_ADDR
bool
config ARCH_PHYS_ADDR_T_64BIT
def_bool 64BIT_PHYS_ADDR
bool
config CPU_HAS_SMARTMIPS
depends on SYS_SUPPORTS_SMARTMIPS
...
...
arch/mips/alchemy/common/setup.c
浏览文件 @
34adb28d
...
...
@@ -70,7 +70,7 @@ void __init plat_mem_setup(void)
iomem_resource
.
end
=
IOMEM_RESOURCE_END
;
}
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_PCI)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_PCI)
/* This routine should be valid for all Au1x based boards */
phys_t
__fixup_bigphys_addr
(
phys_t
phys_addr
,
phys_t
size
)
{
...
...
arch/mips/include/asm/mach-au1x00/ioremap.h
浏览文件 @
34adb28d
...
...
@@ -11,7 +11,7 @@
#include <linux/types.h>
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_PCI)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_PCI)
extern
phys_t
__fixup_bigphys_addr
(
phys_t
,
phys_t
);
#else
static
inline
phys_t
__fixup_bigphys_addr
(
phys_t
phys_addr
,
phys_t
size
)
...
...
arch/mips/include/asm/page.h
浏览文件 @
34adb28d
...
...
@@ -116,7 +116,7 @@ extern void copy_user_highpage(struct page *to, struct page *from,
/*
* These are used to make use of C type-checking..
*/
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
#ifdef CONFIG_CPU_MIPS32
typedef
struct
{
unsigned
long
pte_low
,
pte_high
;
}
pte_t
;
#define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
...
...
arch/mips/include/asm/pgtable-32.h
浏览文件 @
34adb28d
...
...
@@ -69,7 +69,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
#endif
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
#define pte_ERROR(e) \
printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
#else
...
...
@@ -103,7 +103,7 @@ static inline void pmd_clear(pmd_t *pmdp)
pmd_val
(
*
pmdp
)
=
((
unsigned
long
)
invalid_pte_table
);
}
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
#define pte_page(x) pfn_to_page(pte_pfn(x))
#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
static
inline
pte_t
...
...
@@ -126,7 +126,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
#endif
#endif
/* defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32) */
#endif
/* defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32) */
#define __pgd_offset(address) pgd_index(address)
#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
...
...
@@ -177,7 +177,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
#else
/* Swap entries must have VALID and GLOBAL bits cleared. */
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
#define __swp_type(x) (((x).val >> 2) & 0x1f)
#define __swp_offset(x) ((x).val >> 7)
#define __swp_entry(type,offset) \
...
...
@@ -187,9 +187,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
#define __swp_offset(x) ((x).val >> 13)
#define __swp_entry(type,offset) \
((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
#endif
/* defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32) */
#endif
/* defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32) */
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
/*
* Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
*/
...
...
@@ -216,7 +216,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
#endif
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
#else
...
...
arch/mips/include/asm/pgtable-bits.h
浏览文件 @
34adb28d
...
...
@@ -32,7 +32,7 @@
* unpredictable things. The code (when it is written) to deal with
* this problem will be in the update_mmu_cache() code for the r4k.
*/
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
/*
* The following bits are directly used by the TLB hardware
...
...
@@ -172,7 +172,7 @@
#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
#endif
/* defined(CONFIG_
64BIT_PHYS_ADDR
&& defined(CONFIG_CPU_MIPS32) */
#endif
/* defined(CONFIG_
PHYS_ADDR_T_64BIT
&& defined(CONFIG_CPU_MIPS32) */
#ifndef _PFN_SHIFT
#define _PFN_SHIFT PAGE_SHIFT
...
...
arch/mips/include/asm/pgtable.h
浏览文件 @
34adb28d
...
...
@@ -125,7 +125,7 @@ do { \
extern
void
set_pte_at
(
struct
mm_struct
*
mm
,
unsigned
long
addr
,
pte_t
*
ptep
,
pte_t
pteval
);
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
...
...
@@ -227,7 +227,7 @@ extern pgd_t swapper_pg_dir[];
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
static
inline
int
pte_write
(
pte_t
pte
)
{
return
pte
.
pte_low
&
_PAGE_WRITE
;
}
static
inline
int
pte_dirty
(
pte_t
pte
)
{
return
pte
.
pte_low
&
_PAGE_MODIFIED
;
}
static
inline
int
pte_young
(
pte_t
pte
)
{
return
pte
.
pte_low
&
_PAGE_ACCESSED
;
}
...
...
@@ -382,7 +382,7 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
*/
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
static
inline
pte_t
pte_modify
(
pte_t
pte
,
pgprot_t
newprot
)
{
pte
.
pte_low
&=
_PAGE_CHG_MASK
;
...
...
@@ -419,7 +419,7 @@ static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
#define kern_addr_valid(addr) (1)
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
extern
int
remap_pfn_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
pfn
,
unsigned
long
size
,
pgprot_t
prot
);
static
inline
int
io_remap_pfn_range
(
struct
vm_area_struct
*
vma
,
...
...
arch/mips/include/asm/types.h
浏览文件 @
34adb28d
...
...
@@ -22,7 +22,7 @@
/*
* Don't use phys_t. You've been warned.
*/
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
typedef
unsigned
long
long
phys_t
;
#else
typedef
unsigned
long
phys_t
;
...
...
arch/mips/mm/gup.c
浏览文件 @
34adb28d
...
...
@@ -17,7 +17,7 @@
static
inline
pte_t
gup_get_pte
(
pte_t
*
ptep
)
{
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
pte_t
pte
;
retry:
...
...
arch/mips/mm/init.c
浏览文件 @
34adb28d
...
...
@@ -95,7 +95,7 @@ static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
idx
+=
in_interrupt
()
?
FIX_N_COLOURS
:
0
;
vaddr
=
__fix_to_virt
(
FIX_CMAP_END
-
idx
);
pte
=
mk_pte
(
page
,
prot
);
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
entrylo
=
pte
.
pte_high
;
#else
entrylo
=
pte_to_entrylo
(
pte_val
(
pte
));
...
...
arch/mips/mm/tlb-r4k.c
浏览文件 @
34adb28d
...
...
@@ -332,7 +332,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
{
ptep
=
pte_offset_map
(
pmdp
,
address
);
#if defined(CONFIG_
64BIT_PHYS_ADDR
) && defined(CONFIG_CPU_MIPS32)
#if defined(CONFIG_
PHYS_ADDR_T_64BIT
) && defined(CONFIG_CPU_MIPS32)
write_c0_entrylo0
(
ptep
->
pte_high
);
ptep
++
;
write_c0_entrylo1
(
ptep
->
pte_high
);
...
...
arch/mips/mm/tlbex.c
浏览文件 @
34adb28d
...
...
@@ -637,7 +637,7 @@ static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
if
(
cpu_has_rixi
)
{
UASM_i_ROTR
(
p
,
reg
,
reg
,
ilog2
(
_PAGE_GLOBAL
));
}
else
{
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
uasm_i_dsrl_safe
(
p
,
reg
,
reg
,
ilog2
(
_PAGE_GLOBAL
));
#else
UASM_i_SRL
(
p
,
reg
,
reg
,
ilog2
(
_PAGE_GLOBAL
));
...
...
@@ -1009,7 +1009,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
* 64bit address support (36bit on a 32bit CPU) in a 32bit
* Kernel is a special case. Only a few CPUs use it.
*/
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
if
(
cpu_has_64bits
)
{
uasm_i_ld
(
p
,
tmp
,
0
,
ptep
);
/* get even pte */
uasm_i_ld
(
p
,
ptep
,
sizeof
(
pte_t
),
ptep
);
/* get odd pte */
...
...
@@ -1510,14 +1510,14 @@ static void
iPTE_LW
(
u32
**
p
,
unsigned
int
pte
,
unsigned
int
ptr
)
{
#ifdef CONFIG_SMP
# ifdef CONFIG_
64BIT_PHYS_ADDR
# ifdef CONFIG_
PHYS_ADDR_T_64BIT
if
(
cpu_has_64bits
)
uasm_i_lld
(
p
,
pte
,
0
,
ptr
);
else
# endif
UASM_i_LL
(
p
,
pte
,
0
,
ptr
);
#else
# ifdef CONFIG_
64BIT_PHYS_ADDR
# ifdef CONFIG_
PHYS_ADDR_T_64BIT
if
(
cpu_has_64bits
)
uasm_i_ld
(
p
,
pte
,
0
,
ptr
);
else
...
...
@@ -1530,13 +1530,13 @@ static void
iPTE_SW
(
u32
**
p
,
struct
uasm_reloc
**
r
,
unsigned
int
pte
,
unsigned
int
ptr
,
unsigned
int
mode
)
{
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
unsigned
int
hwmode
=
mode
&
(
_PAGE_VALID
|
_PAGE_DIRTY
);
#endif
uasm_i_ori
(
p
,
pte
,
pte
,
mode
);
#ifdef CONFIG_SMP
# ifdef CONFIG_
64BIT_PHYS_ADDR
# ifdef CONFIG_
PHYS_ADDR_T_64BIT
if
(
cpu_has_64bits
)
uasm_i_scd
(
p
,
pte
,
0
,
ptr
);
else
...
...
@@ -1548,7 +1548,7 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
else
uasm_il_beqz
(
p
,
r
,
pte
,
label_smp_pgtable_change
);
# ifdef CONFIG_
64BIT_PHYS_ADDR
# ifdef CONFIG_
PHYS_ADDR_T_64BIT
if
(
!
cpu_has_64bits
)
{
/* no uasm_i_nop needed */
uasm_i_ll
(
p
,
pte
,
sizeof
(
pte_t
)
/
2
,
ptr
);
...
...
@@ -1563,14 +1563,14 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
uasm_i_nop
(
p
);
# endif
#else
# ifdef CONFIG_
64BIT_PHYS_ADDR
# ifdef CONFIG_
PHYS_ADDR_T_64BIT
if
(
cpu_has_64bits
)
uasm_i_sd
(
p
,
pte
,
0
,
ptr
);
else
# endif
UASM_i_SW
(
p
,
pte
,
0
,
ptr
);
# ifdef CONFIG_
64BIT_PHYS_ADDR
# ifdef CONFIG_
PHYS_ADDR_T_64BIT
if
(
!
cpu_has_64bits
)
{
uasm_i_lw
(
p
,
pte
,
sizeof
(
pte_t
)
/
2
,
ptr
);
uasm_i_ori
(
p
,
pte
,
pte
,
hwmode
);
...
...
arch/mips/sibyte/common/cfe.c
浏览文件 @
34adb28d
...
...
@@ -38,7 +38,7 @@
#define MAX_RAM_SIZE (~0ULL)
#else
#ifdef CONFIG_HIGHMEM
#ifdef CONFIG_
64BIT_PHYS_ADDR
#ifdef CONFIG_
PHYS_ADDR_T_64BIT
#define MAX_RAM_SIZE (~0ULL)
#else
#define MAX_RAM_SIZE (0xffffffffULL)
...
...
@@ -96,7 +96,7 @@ static void __noreturn cfe_linux_halt(void)
static
__init
void
prom_meminit
(
void
)
{
u64
addr
,
size
,
type
;
/* regardless of
64BIT_PHYS_ADDR
*/
u64
addr
,
size
,
type
;
/* regardless of
PHYS_ADDR_T_64BIT
*/
int
mem_flags
=
0
;
unsigned
int
idx
;
int
rd_flag
;
...
...
drivers/dma/txx9dmac.c
浏览文件 @
34adb28d
...
...
@@ -76,7 +76,7 @@ static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
static
void
channel64_clear_CHAR
(
const
struct
txx9dmac_chan
*
dc
)
{
#if defined(CONFIG_32BIT) && !defined(CONFIG_
64BIT_PHYS_ADDR
)
#if defined(CONFIG_32BIT) && !defined(CONFIG_
PHYS_ADDR_T_64BIT
)
channel64_writel
(
dc
,
CHAR
,
0
);
channel64_writel
(
dc
,
__pad_CHAR
,
0
);
#else
...
...
drivers/dma/txx9dmac.h
浏览文件 @
34adb28d
...
...
@@ -67,7 +67,7 @@ static inline bool txx9_dma_have_SMPCHN(void)
/* Hardware register definitions. */
struct
txx9dmac_cregs
{
#if defined(CONFIG_32BIT) && !defined(CONFIG_
64BIT_PHYS_ADDR
)
#if defined(CONFIG_32BIT) && !defined(CONFIG_
PHYS_ADDR_T_64BIT
)
TXX9_DMA_REG32
(
CHAR
);
/* Chain Address Register */
#else
u64
CHAR
;
/* Chain Address Register */
...
...
@@ -201,7 +201,7 @@ static inline bool is_dmac64(const struct txx9dmac_chan *dc)
#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
/* Hardware descriptor definition. (for simple-chain) */
struct
txx9dmac_hwdesc
{
#if defined(CONFIG_32BIT) && !defined(CONFIG_
64BIT_PHYS_ADDR
)
#if defined(CONFIG_32BIT) && !defined(CONFIG_
PHYS_ADDR_T_64BIT
)
TXX9_DMA_REG32
(
CHAR
);
#else
u64
CHAR
;
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录