drm/amd/display: Add DCN2 DWB

Add support to program the DCN2 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dc_types.h

@@ -421,6 +421,32 @@ enum display_content_type {
 	DISPLAY_CONTENT_TYPE_GAME = 8
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+/* writeback */
+struct dc_dwb_cnv_params {
+	unsigned int		src_width;	/* input active width */
+	unsigned int		src_height;	/* input active height (half-active height in interlaced mode) */
+	unsigned int		crop_width;	/* cropped window width at cnv output */
+	bool			crop_en;	/* window cropping enable in cnv */
+	unsigned int		crop_height;	/* cropped window height at cnv output */
+	unsigned int		crop_x;		/* cropped window start x value at cnv output */
+	unsigned int		crop_y;		/* cropped window start y value at cnv output */
+	enum dwb_cnv_out_bpc cnv_out_bpc;	/* cnv output pixel depth - 8bpc or 10bpc */
+};
+
+struct dc_dwb_params {
+	struct dc_dwb_cnv_params	cnv_params;	/* CNV source size and cropping window parameters */
+	unsigned int			dest_width;	/* Destination width */
+	unsigned int			dest_height;	/* Destination height */
+	enum dwb_scaler_mode		out_format;	/* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
+	enum dwb_output_depth		output_depth;	/* output pixel depth - 8bpc or 10bpc */
+	enum dwb_capture_rate		capture_rate;	/* controls the frame capture rate */
+	struct scaling_taps 		scaler_taps;	/* Scaling taps */
+	enum dwb_subsample_position	subsample_position;
+	struct dc_transfer_func *out_transfer_func;
+};
+#endif
+
 /* audio*/
 
 union audio_sample_rates {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

+/*
+ * Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+
+#include "reg_helper.h"
+#include "resource.h"
+#include "dwb.h"
+#include "dcn10_dwb.h"
+
+
+#define REG(reg)\
+	dwbc10->dwbc_regs->reg
+
+#define CTX \
+	dwbc10->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
+
+#define TO_DCN10_DWBC(dwbc_base) \
+	container_of(dwbc_base, struct dcn10_dwbc, base)
+
+static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
+{
+	if (caps) {
+		caps->adapter_id = 0;	/* we only support 1 adapter currently */
+		caps->hw_version = DCN_VERSION_1_0;
+		caps->num_pipes = 2;
+		memset(&caps->reserved, 0, sizeof(caps->reserved));
+		memset(&caps->reserved2, 0, sizeof(caps->reserved2));
+		caps->sw_version = dwb_ver_1_0;
+		caps->caps.support_dwb = true;
+		caps->caps.support_ogam = false;
+		caps->caps.support_wbscl = true;
+		caps->caps.support_ocsc = false;
+		return true;
+	} else {
+		return false;
+	}
+}
+
+static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+	struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
+
+	/* disable first. */
+	dwbc->funcs->disable(dwbc);
+
+	/* disable power gating */
+	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
+		 DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,
+		 WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);
+
+	REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
+
+	return true;
+}
+
+static bool dwb1_disable(struct dwbc *dwbc)
+{
+	struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
+
+	/* disable CNV */
+	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);
+
+	/* disable WB */
+	REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
+
+	/* soft reset */
+	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
+	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
+
+	/* enable power gating */
+	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
+		 DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,
+		 WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);
+
+	return true;
+}
+
+const struct dwbc_funcs dcn10_dwbc_funcs = {
+	.get_caps			= dwb1_get_caps,
+	.enable				= dwb1_enable,
+	.disable			= dwb1_disable,
+	.update				= NULL,
+	.set_stereo			= NULL,
+	.set_new_content		= NULL,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+	.set_warmup			= NULL,
+#endif
+	.dwb_set_scaler			= NULL,
+};
+
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+		struct dc_context *ctx,
+		const struct dcn10_dwbc_registers *dwbc_regs,
+		const struct dcn10_dwbc_shift *dwbc_shift,
+		const struct dcn10_dwbc_mask *dwbc_mask,
+		int inst)
+{
+	dwbc10->base.ctx = ctx;
+
+	dwbc10->base.inst = inst;
+	dwbc10->base.funcs = &dcn10_dwbc_funcs;
+
+	dwbc10->dwbc_regs = dwbc_regs;
+	dwbc10->dwbc_shift = dwbc_shift;
+	dwbc10->dwbc_mask = dwbc_mask;
+}
+
+
+#endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_DWBC_DCN10_H__
+#define __DC_DWBC_DCN10_H__
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+
+/* DCN */
+#define BASE_INNER(seg) \
+	DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
+					mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+
+#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
+	SRI(WB_ENABLE, CNV, inst),\
+	SRI(WB_EC_CONFIG, CNV, inst),\
+	SRI(CNV_MODE, CNV, inst),\
+	SRI(WB_SOFT_RESET, CNV, inst),\
+	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
+	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
+	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
+	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
+
+#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
+	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
+	SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh)
+
+#define DWBC_REG_FIELD_LIST(type) \
+	type WB_ENABLE;\
+	type DISPCLK_R_WB_GATE_DIS;\
+	type DISPCLK_G_WB_GATE_DIS;\
+	type DISPCLK_G_WBSCL_GATE_DIS;\
+	type WB_LB_LS_DIS;\
+	type WB_LB_SD_DIS;\
+	type WB_LUT_LS_DIS;\
+	type CNV_WINDOW_CROP_EN;\
+	type CNV_STEREO_TYPE;\
+	type CNV_INTERLACED_MODE;\
+	type CNV_EYE_SELECTION;\
+	type CNV_STEREO_POLARITY;\
+	type CNV_INTERLACED_FIELD_ORDER;\
+	type CNV_STEREO_SPLIT;\
+	type CNV_NEW_CONTENT;\
+	type CNV_FRAME_CAPTURE_EN;\
+	type WB_SOFT_RESET;\
+	type MCIF_WB_BUFMGR_ENABLE;\
+	type MCIF_WB_BUF_DUALSIZE_REQ;\
+	type MCIF_WB_BUFMGR_SW_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_INT_ACK;\
+	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_LOCK;\
+	type MCIF_WB_P_VMID;\
+	type MCIF_WB_BUF_ADDR_FENCE_EN;\
+	type MCIF_WB_BUF_LUMA_PITCH;\
+	type MCIF_WB_BUF_CHROMA_PITCH;\
+	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
+	type MCIF_WB_TIME_PER_PIXEL;\
+	type WM_CHANGE_ACK_FORCE_ON;\
+	type MCIF_WB_CLI_WATERMARK_MASK;\
+	type MCIF_WB_BUF_1_ADDR_Y;\
+	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_1_ADDR_C;\
+	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_2_ADDR_Y;\
+	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_2_ADDR_C;\
+	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_3_ADDR_Y;\
+	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_3_ADDR_C;\
+	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_4_ADDR_Y;\
+	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_4_ADDR_C;\
+	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
+	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
+	type MCIF_WB_BUFMGR_VCE_INT_EN;\
+	type MCIF_WB_BUFMGR_VCE_INT_ACK;\
+	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
+	type MCIF_WB_BUFMGR_VCE_LOCK;\
+	type MCIF_WB_BUFMGR_SLICE_SIZE;\
+	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
+	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
+	type NB_PSTATE_CHANGE_FORCE_ON;\
+	type NB_PSTATE_ALLOW_FOR_URGENT;\
+	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
+	type MCIF_WB_CLI_WATERMARK;\
+	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
+	type MCIF_WB_PITCH_SIZE_WARMUP;\
+	type MCIF_WB_BUF_LUMA_SIZE;\
+	type MCIF_WB_BUF_CHROMA_SIZE;\
+
+struct dcn10_dwbc_registers {
+	uint32_t WB_ENABLE;
+	uint32_t WB_EC_CONFIG;
+	uint32_t CNV_MODE;
+	uint32_t WB_SOFT_RESET;
+	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
+	uint32_t MCIF_WB_BUF_PITCH;
+	uint32_t MCIF_WB_ARBITRATION_CONTROL;
+	uint32_t MCIF_WB_SCLK_CHANGE;
+	uint32_t MCIF_WB_BUF_1_ADDR_Y;
+	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_1_ADDR_C;
+	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_2_ADDR_Y;
+	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_2_ADDR_C;
+	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_3_ADDR_Y;
+	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_3_ADDR_C;
+	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_4_ADDR_Y;
+	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_4_ADDR_C;
+	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
+	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
+	uint32_t MCIF_WB_NB_PSTATE_CONTROL;
+	uint32_t MCIF_WB_WATERMARK;
+	uint32_t MCIF_WB_WARM_UP_CNTL;
+	uint32_t MCIF_WB_BUF_LUMA_SIZE;
+	uint32_t MCIF_WB_BUF_CHROMA_SIZE;
+};
+struct dcn10_dwbc_mask {
+	DWBC_REG_FIELD_LIST(uint32_t)
+};
+struct dcn10_dwbc_shift {
+	DWBC_REG_FIELD_LIST(uint8_t)
+};
+struct dcn10_dwbc {
+	struct dwbc base;
+	const struct dcn10_dwbc_registers *dwbc_regs;
+	const struct dcn10_dwbc_shift *dwbc_shift;
+	const struct dcn10_dwbc_mask *dwbc_mask;
+};
+
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+		struct dc_context *ctx,
+		const struct dcn10_dwbc_registers *dwbc_regs,
+		const struct dcn10_dwbc_shift *dwbc_shift,
+		const struct dcn10_dwbc_mask *dwbc_mask,
+		int inst);
+
+#endif
+
+#endif

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

+/*
+ * Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+#include "resource.h"
+#include "dwb.h"
+#include "dcn20_dwb.h"
+
+
+#define REG(reg)\
+	dwbc20->dwbc_regs->reg
+
+#define CTX \
+	dwbc20->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
+
+enum dwb_outside_pix_strategy {
+	DWB_OUTSIDE_PIX_STRATEGY_BLACK = 0,
+	DWB_OUTSIDE_PIX_STRATEGY_EDGE  = 1
+};
+
+static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
+{
+	if (caps) {
+		caps->adapter_id = 0;	/* we only support 1 adapter currently */
+		caps->hw_version = DCN_VERSION_2_0;
+		caps->num_pipes = 1;
+		memset(&caps->reserved, 0, sizeof(caps->reserved));
+		memset(&caps->reserved2, 0, sizeof(caps->reserved2));
+		caps->sw_version = dwb_ver_1_0;
+		caps->caps.support_dwb = true;
+		caps->caps.support_ogam = false;
+		caps->caps.support_wbscl = false;
+		caps->caps.support_ocsc = false;
+		return true;
+	} else {
+		return false;
+	}
+}
+
+void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+	/* Set DWB source size */
+	REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width,
+			CNV_SOURCE_HEIGHT, params->cnv_params.src_height);
+
+	/* source size is not equal the source size, then enable cropping. */
+	if (params->cnv_params.crop_en) {
+		REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1);
+		REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x);
+		REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y);
+		REG_UPDATE(CNV_WINDOW_SIZE,  CNV_WINDOW_WIDTH,   params->cnv_params.crop_width);
+		REG_UPDATE(CNV_WINDOW_SIZE,  CNV_WINDOW_HEIGHT,  params->cnv_params.crop_height);
+	} else {
+		REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0);
+	}
+
+	/* Set CAPTURE_RATE */
+	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate);
+
+	/* Set CNV output pixel depth */
+	REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc);
+}
+
+static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+	/* Only chroma scaling (sub-sampling) is supported in DCN2 */
+	if ((params->cnv_params.src_width  != params->dest_width)
+	 || (params->cnv_params.src_height != params->dest_height)) {
+		return false;
+	}
+
+	/* disable power gating */
+	//REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
+	//			 DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,
+	//			 WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);
+
+	/* Set WB_ENABLE (not double buffered; capture not enabled) */
+	REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
+
+	/* Set CNV parameters */
+	dwb2_config_dwb_cnv(dwbc, params);
+
+	/* Set scaling parameters */
+	dwb2_set_scaler(dwbc, params);
+
+	/* Enable DWB capture enable (double buffered) */
+	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE);
+
+	// disable warmup
+	REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, 0);
+
+	return true;
+}
+
+bool dwb2_disable(struct dwbc *dwbc)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+	/* disable CNV */
+	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);
+
+	/* disable WB */
+	REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
+
+	/* soft reset */
+	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
+	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
+
+	/* enable power gating */
+	//REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
+	//			 DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,
+	//			 WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);
+
+	return true;
+}
+
+static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+	unsigned int pre_locked;
+
+	/* Only chroma scaling (sub-sampling) is supported in DCN2 */
+	if ((params->cnv_params.src_width  != params->dest_width)
+			|| (params->cnv_params.src_height != params->dest_height)) {
+		return false;
+	}
+
+	/*
+	 * Check if the caller has already locked CNV registers.
+	 * If so: assume the caller will unlock, so don't touch the lock.
+	 * If not: lock them for this update, then unlock after the
+	 * update is complete.
+	 */
+	REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked);
+
+	if (pre_locked == 0) {
+		/* Lock DWB registers */
+		REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 1);
+	}
+
+	/* Set CNV parameters */
+	dwb2_config_dwb_cnv(dwbc, params);
+
+	/* Set scaling parameters */
+	dwb2_set_scaler(dwbc, params);
+
+	if (pre_locked == 0) {
+		/* Unlock DWB registers */
+		REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 0);
+	}
+
+	return true;
+}
+
+bool dwb2_is_enabled(struct dwbc *dwbc)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+	unsigned int wb_enabled = 0;
+	unsigned int cnv_frame_capture_en = 0;
+
+	REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled);
+	REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en);
+
+	return ((wb_enabled != 0) && (cnv_frame_capture_en != 0));
+}
+
+void dwb2_set_stereo(struct dwbc *dwbc,
+		struct dwb_stereo_params *stereo_params)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+	if (stereo_params->stereo_enabled) {
+		REG_UPDATE(CNV_MODE, CNV_STEREO_TYPE,     stereo_params->stereo_type);
+		REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION,   stereo_params->stereo_eye_select);
+		REG_UPDATE(CNV_MODE, CNV_STEREO_POLARITY, stereo_params->stereo_polarity);
+	} else {
+		REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION, 0);
+	}
+}
+
+void dwb2_set_new_content(struct dwbc *dwbc,
+						bool is_new_content)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+	REG_UPDATE(CNV_MODE, CNV_NEW_CONTENT, is_new_content);
+}
+
+static void dwb2_set_warmup(struct dwbc *dwbc,
+		struct dwb_warmup_params *warmup_params)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+	REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, warmup_params->warmup_en);
+	REG_UPDATE(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, warmup_params->warmup_width);
+	REG_UPDATE(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, warmup_params->warmup_height);
+
+	REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, warmup_params->warmup_data);
+	REG_UPDATE(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, warmup_params->warmup_mode);
+	REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, warmup_params->warmup_depth);
+}
+
+void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+	/* Program scaling mode */
+	REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format,
+			WBSCL_OUT_BIT_DEPTH, params->output_depth);
+
+	if (params->out_format != dwb_scaler_mode_bypass444) {
+		/* Program output size */
+		REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH,	params->dest_width);
+		REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT,	params->dest_height);
+
+		/* Program round offsets */
+		REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, 0x40);
+		REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR,  0x200);
+
+		/* Program clamp values */
+		REG_UPDATE(WBSCL_CLAMP_Y_RGB,	WBSCL_CLAMP_UPPER_Y_RGB,	0x3fe);
+		REG_UPDATE(WBSCL_CLAMP_Y_RGB,	WBSCL_CLAMP_LOWER_Y_RGB,	0x1);
+		REG_UPDATE(WBSCL_CLAMP_CBCR,	WBSCL_CLAMP_UPPER_CBCR,		0x3fe);
+		REG_UPDATE(WBSCL_CLAMP_CBCR,	WBSCL_CLAMP_LOWER_CBCR,		0x1);
+
+		/* Program outside pixel strategy to use edge pixels */
+		REG_UPDATE(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, DWB_OUTSIDE_PIX_STRATEGY_EDGE);
+
+		if (params->cnv_params.crop_en) {
+			/* horizontal scale */
+			dwb_program_horz_scalar(dwbc20, params->cnv_params.crop_width,
+							params->dest_width,
+							params->scaler_taps);
+
+			/* vertical scale */
+			dwb_program_vert_scalar(dwbc20, params->cnv_params.crop_height,
+							params->dest_height,
+							params->scaler_taps,
+							params->subsample_position);
+		} else {
+			/* horizontal scale */
+			dwb_program_horz_scalar(dwbc20, params->cnv_params.src_width,
+							params->dest_width,
+							params->scaler_taps);
+
+			/* vertical scale */
+			dwb_program_vert_scalar(dwbc20, params->cnv_params.src_height,
+							params->dest_height,
+							params->scaler_taps,
+							params->subsample_position);
+		}
+	}
+
+}
+
+const struct dwbc_funcs dcn20_dwbc_funcs = {
+	.get_caps		= dwb2_get_caps,
+	.enable			= dwb2_enable,
+	.disable		= dwb2_disable,
+	.update			= dwb2_update,
+	.is_enabled		= dwb2_is_enabled,
+	.set_stereo		= dwb2_set_stereo,
+	.set_new_content	= dwb2_set_new_content,
+	.set_warmup		= dwb2_set_warmup,
+	.dwb_set_scaler		= dwb2_set_scaler,
+};
+
+void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
+		struct dc_context *ctx,
+		const struct dcn20_dwbc_registers *dwbc_regs,
+		const struct dcn20_dwbc_shift *dwbc_shift,
+		const struct dcn20_dwbc_mask *dwbc_mask,
+		int inst)
+{
+	dwbc20->base.ctx = ctx;
+
+	dwbc20->base.inst = inst;
+	dwbc20->base.funcs = &dcn20_dwbc_funcs;
+
+	dwbc20->dwbc_regs = dwbc_regs;
+	dwbc20->dwbc_shift = dwbc_shift;
+	dwbc20->dwbc_mask = dwbc_mask;
+}
+

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_DWBC_DCN20_H__
+#define __DC_DWBC_DCN20_H__
+
+#define TO_DCN20_DWBC(dwbc_base) \
+	container_of(dwbc_base, struct dcn20_dwbc, base)
+
+/* DCN */
+#define BASE_INNER(seg) \
+	DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
+					mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+					mm ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+
+#define DWBC_COMMON_REG_LIST_DCN2_0(inst) \
+	SRI2(WB_ENABLE, CNV, inst),\
+	SRI2(WB_EC_CONFIG, CNV, inst),\
+	SRI2(CNV_MODE, CNV, inst),\
+	SRI2(CNV_WINDOW_START, CNV, inst),\
+	SRI2(CNV_WINDOW_SIZE, CNV, inst),\
+	SRI2(CNV_UPDATE, CNV, inst),\
+	SRI2(CNV_SOURCE_SIZE, CNV, inst),\
+	SRI2(CNV_TEST_CNTL, CNV, inst),\
+	SRI2(CNV_TEST_CRC_RED, CNV, inst),\
+	SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\
+	SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\
+	SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
+	SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
+	SRI2(WBSCL_MODE, WBSCL, inst),\
+	SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\
+	SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\
+	SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
+	SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
+	SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
+	SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
+	SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
+	SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
+	SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\
+	SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
+	SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
+	SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\
+	SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\
+	SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
+	SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
+	SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
+	SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
+	SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
+	SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\
+	SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
+	SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
+	SRI2(WBSCL_DEBUG, WBSCL, inst),\
+	SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
+	SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
+	SRI2(WB_DEBUG_CTRL, CNV, inst),\
+	SRI2(WB_DBG_MODE, CNV, inst),\
+	SRI2(WB_HW_DEBUG, CNV, inst),\
+	SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\
+	SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\
+	SRI2(WB_SOFT_RESET, CNV, inst),\
+	SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\
+	SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst)
+
+#define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
+	SF(WB_ENABLE, WB_ENABLE, mask_sh),\
+	SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
+	SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
+	SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
+	SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
+	SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
+	SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
+	SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
+	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
+	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
+	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
+	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
+	SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
+	SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
+	SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
+	SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
+	SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
+	SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
+	SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
+	SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
+	SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
+	SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
+	SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
+	SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
+	SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
+	SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
+	SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
+	SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
+	SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
+	SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
+	SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
+	SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
+	SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
+	SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
+	SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
+	SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
+	SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
+	SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
+	SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
+	SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
+	SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
+	SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
+	SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
+	SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
+	SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
+	SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
+	SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
+	SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
+	SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
+	SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
+	SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
+	SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
+	SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
+	SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
+	SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
+	SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
+	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
+	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
+	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
+	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
+	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
+	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
+	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
+	SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
+	SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
+	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
+	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
+	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
+	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
+	SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
+	SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
+	SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
+	SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
+	SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
+	SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
+	SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
+	SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
+	SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
+	SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
+	SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
+	SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
+	SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
+	SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
+	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
+	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
+	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
+	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
+	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
+	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
+	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
+	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
+	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
+	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
+	SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
+	SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
+	SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
+	SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
+	SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
+	SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
+	SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
+	SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
+	SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
+	SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
+	SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
+	SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
+	SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
+	SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
+	SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
+	SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
+	SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
+	SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
+	SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
+	SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
+	SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
+	SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
+	SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
+	SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
+	SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
+	SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
+	SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
+	SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
+	SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)
+
+#define DWBC_REG_FIELD_LIST_DCN2_0(type) \
+	type WB_ENABLE;\
+	type DISPCLK_R_WB_GATE_DIS;\
+	type DISPCLK_G_WB_GATE_DIS;\
+	type DISPCLK_G_WBSCL_GATE_DIS;\
+	type WB_TEST_CLK_SEL;\
+	type WB_LB_LS_DIS;\
+	type WB_LB_SD_DIS;\
+	type WB_LUT_LS_DIS;\
+	type WBSCL_LB_MEM_PWR_MODE_SEL;\
+	type WBSCL_LB_MEM_PWR_DIS;\
+	type WBSCL_LB_MEM_PWR_FORCE;\
+	type WBSCL_LB_MEM_PWR_STATE;\
+	type WB_RAM_PW_SAVE_MODE;\
+	type WBSCL_LUT_MEM_PWR_STATE;\
+	type CNV_OUT_BPC;\
+	type CNV_FRAME_CAPTURE_RATE;\
+	type CNV_WINDOW_CROP_EN;\
+	type CNV_STEREO_TYPE;\
+	type CNV_INTERLACED_MODE;\
+	type CNV_EYE_SELECTION;\
+	type CNV_STEREO_POLARITY;\
+	type CNV_INTERLACED_FIELD_ORDER;\
+	type CNV_STEREO_SPLIT;\
+	type CNV_NEW_CONTENT;\
+	type CNV_FRAME_CAPTURE_EN_CURRENT;\
+	type CNV_FRAME_CAPTURE_EN;\
+	type CNV_WINDOW_START_X;\
+	type CNV_WINDOW_START_Y;\
+	type CNV_WINDOW_WIDTH;\
+	type CNV_WINDOW_HEIGHT;\
+	type CNV_UPDATE_PENDING;\
+	type CNV_UPDATE_TAKEN;\
+	type CNV_UPDATE_LOCK;\
+	type CNV_SOURCE_WIDTH;\
+	type CNV_SOURCE_HEIGHT;\
+	type CNV_TEST_CRC_EN;\
+	type CNV_TEST_CRC_CONT_EN;\
+	type CNV_TEST_CRC_RED_MASK;\
+	type CNV_TEST_CRC_SIG_RED;\
+	type CNV_TEST_CRC_GREEN_MASK;\
+	type CNV_TEST_CRC_SIG_GREEN;\
+	type CNV_TEST_CRC_BLUE_MASK;\
+	type CNV_TEST_CRC_SIG_BLUE;\
+	type WB_DEBUG_EN;\
+	type WB_DEBUG_SEL;\
+	type WB_DBG_MODE_EN;\
+	type WB_DBG_DIN_FMT;\
+	type WB_DBG_36MODE;\
+	type WB_DBG_CMAP;\
+	type WB_DBG_PXLRATE_ERROR;\
+	type WB_DBG_SOURCE_WIDTH;\
+	type WB_HW_DEBUG;\
+	type CNV_TEST_DEBUG_INDEX;\
+	type CNV_TEST_DEBUG_WRITE_EN;\
+	type CNV_TEST_DEBUG_DATA;\
+	type WB_SOFT_RESET;\
+	type WBSCL_COEF_RAM_TAP_PAIR_IDX;\
+	type WBSCL_COEF_RAM_PHASE;\
+	type WBSCL_COEF_RAM_FILTER_TYPE;\
+	type WBSCL_COEF_RAM_SEL;\
+	type WBSCL_COEF_RAM_SEL_CURRENT;\
+	type WBSCL_COEF_RAM_RD_SEL;\
+	type WBSCL_COEF_RAM_EVEN_TAP_COEF;\
+	type WBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\
+	type WBSCL_COEF_RAM_ODD_TAP_COEF;\
+	type WBSCL_COEF_RAM_ODD_TAP_COEF_EN;\
+	type WBSCL_MODE;\
+	type WBSCL_OUT_BIT_DEPTH;\
+	type WBSCL_V_NUM_OF_TAPS_Y_RGB;\
+	type WBSCL_V_NUM_OF_TAPS_CBCR;\
+	type WBSCL_H_NUM_OF_TAPS_Y_RGB;\
+	type WBSCL_H_NUM_OF_TAPS_CBCR;\
+	type WBSCL_DEST_HEIGHT;\
+	type WBSCL_DEST_WIDTH;\
+	type WBSCL_H_SCALE_RATIO;\
+	type WBSCL_H_INIT_FRAC_Y_RGB;\
+	type WBSCL_H_INIT_INT_Y_RGB;\
+	type WBSCL_H_INIT_FRAC_CBCR;\
+	type WBSCL_H_INIT_INT_CBCR;\
+	type WBSCL_V_SCALE_RATIO;\
+	type WBSCL_V_INIT_FRAC_Y_RGB;\
+	type WBSCL_V_INIT_INT_Y_RGB;\
+	type WBSCL_V_INIT_FRAC_CBCR;\
+	type WBSCL_V_INIT_INT_CBCR;\
+	type WBSCL_ROUND_OFFSET_Y_RGB;\
+	type WBSCL_ROUND_OFFSET_CBCR;\
+	type WBSCL_DATA_OVERFLOW_FLAG;\
+	type WBSCL_DATA_OVERFLOW_ACK;\
+	type WBSCL_DATA_OVERFLOW_MASK;\
+	type WBSCL_DATA_OVERFLOW_INT_STATUS;\
+	type WBSCL_DATA_OVERFLOW_INT_TYPE;\
+	type WBSCL_HOST_CONFLICT_FLAG;\
+	type WBSCL_HOST_CONFLICT_ACK;\
+	type WBSCL_HOST_CONFLICT_MASK;\
+	type WBSCL_HOST_CONFLICT_INT_STATUS;\
+	type WBSCL_HOST_CONFLICT_INT_TYPE;\
+	type WBSCL_TEST_CRC_EN;\
+	type WBSCL_TEST_CRC_CONT_EN;\
+	type WBSCL_TEST_CRC_RED_MASK;\
+	type WBSCL_TEST_CRC_SIG_RED;\
+	type WBSCL_TEST_CRC_GREEN_MASK;\
+	type WBSCL_TEST_CRC_SIG_GREEN;\
+	type WBSCL_TEST_CRC_BLUE_MASK;\
+	type WBSCL_TEST_CRC_SIG_BLUE;\
+	type WBSCL_BACKPRESSURE_CNT_EN;\
+	type WB_MCIF_Y_MAX_BACKPRESSURE;\
+	type WB_MCIF_C_MAX_BACKPRESSURE;\
+	type WBSCL_CLAMP_UPPER_Y_RGB;\
+	type WBSCL_CLAMP_LOWER_Y_RGB;\
+	type WBSCL_CLAMP_UPPER_CBCR;\
+	type WBSCL_CLAMP_LOWER_CBCR;\
+	type WBSCL_OUTSIDE_PIX_STRATEGY;\
+	type WBSCL_BLACK_COLOR_G_Y;\
+	type WBSCL_BLACK_COLOR_B_CB;\
+	type WBSCL_BLACK_COLOR_R_CR;\
+	type WBSCL_DEBUG;\
+	type WBSCL_TEST_DEBUG_INDEX;\
+	type WBSCL_TEST_DEBUG_WRITE_EN;\
+	type WBSCL_TEST_DEBUG_DATA;\
+	type WIDTH_WARMUP;\
+	type HEIGHT_WARMUP;\
+	type GMC_WARM_UP_ENABLE;\
+	type DATA_VALUE_WARMUP;\
+	type MODE_WARMUP;\
+	type DATA_DEPTH_WARMUP; \
+
+struct dcn20_dwbc_registers {
+	/* DCN2.0 */
+	uint32_t WB_ENABLE;
+	uint32_t WB_EC_CONFIG;
+	uint32_t CNV_MODE;
+	uint32_t CNV_WINDOW_START;
+	uint32_t CNV_WINDOW_SIZE;
+	uint32_t CNV_UPDATE;
+	uint32_t CNV_SOURCE_SIZE;
+	uint32_t CNV_TEST_CNTL;
+	uint32_t CNV_TEST_CRC_RED;
+	uint32_t CNV_TEST_CRC_GREEN;
+	uint32_t CNV_TEST_CRC_BLUE;
+	uint32_t WB_DEBUG_CTRL;
+	uint32_t WB_DBG_MODE;
+	uint32_t WB_HW_DEBUG;
+	uint32_t CNV_TEST_DEBUG_INDEX;
+	uint32_t CNV_TEST_DEBUG_DATA;
+	uint32_t WB_SOFT_RESET;
+	uint32_t WBSCL_COEF_RAM_SELECT;
+	uint32_t WBSCL_COEF_RAM_TAP_DATA;
+	uint32_t WBSCL_MODE;
+	uint32_t WBSCL_TAP_CONTROL;
+	uint32_t WBSCL_DEST_SIZE;
+	uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO;
+	uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB;
+	uint32_t WBSCL_HORZ_FILTER_INIT_CBCR;
+	uint32_t WBSCL_VERT_FILTER_SCALE_RATIO;
+	uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB;
+	uint32_t WBSCL_VERT_FILTER_INIT_CBCR;
+	uint32_t WBSCL_ROUND_OFFSET;
+	uint32_t WBSCL_OVERFLOW_STATUS;
+	uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;
+	uint32_t WBSCL_TEST_CNTL;
+	uint32_t WBSCL_TEST_CRC_RED;
+	uint32_t WBSCL_TEST_CRC_GREEN;
+	uint32_t WBSCL_TEST_CRC_BLUE;
+	uint32_t WBSCL_BACKPRESSURE_CNT_EN;
+	uint32_t WB_MCIF_BACKPRESSURE_CNT;
+	uint32_t WBSCL_CLAMP_Y_RGB;
+	uint32_t WBSCL_CLAMP_CBCR;
+	uint32_t WBSCL_OUTSIDE_PIX_STRATEGY;
+	uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR;
+	uint32_t WBSCL_DEBUG;
+	uint32_t WBSCL_TEST_DEBUG_INDEX;
+	uint32_t WBSCL_TEST_DEBUG_DATA;
+	uint32_t WB_WARM_UP_MODE_CTL1;
+	uint32_t WB_WARM_UP_MODE_CTL2;
+};
+
+
+struct dcn20_dwbc_mask {
+	DWBC_REG_FIELD_LIST_DCN2_0(uint32_t)
+};
+
+struct dcn20_dwbc_shift {
+	DWBC_REG_FIELD_LIST_DCN2_0(uint8_t)
+};
+
+struct dcn20_dwbc {
+	struct dwbc base;
+	const struct dcn20_dwbc_registers *dwbc_regs;
+	const struct dcn20_dwbc_shift *dwbc_shift;
+	const struct dcn20_dwbc_mask *dwbc_mask;
+};
+
+void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
+	struct dc_context *ctx,
+	const struct dcn20_dwbc_registers *dwbc_regs,
+	const struct dcn20_dwbc_shift *dwbc_shift,
+	const struct dcn20_dwbc_mask *dwbc_mask,
+	int inst);
+
+bool dwb2_disable(struct dwbc *dwbc);
+
+bool dwb2_is_enabled(struct dwbc *dwbc);
+
+void dwb2_set_stereo(struct dwbc *dwbc,
+	struct dwb_stereo_params *stereo_params);
+
+void dwb2_set_new_content(struct dwbc *dwbc,
+	bool is_new_content);
+
+void dwb2_config_dwb_cnv(struct dwbc *dwbc,
+	struct dc_dwb_params *params);
+
+void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
+
+bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
+	uint32_t src_height,
+	uint32_t dest_height,
+	struct scaling_taps num_taps,
+	enum dwb_subsample_position subsample_position);
+
+bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
+	uint32_t src_width,
+	uint32_t dest_width,
+	struct scaling_taps num_taps);
+
+
+#endif
+
+

drivers/gpu/drm/amd/display/dc/inc/core_types.h

@@ -36,6 +36,10 @@
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 #include "mpc.h"
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#include "dwb.h"
+#include "mcif_wb.h"
+#endif
 
 #define MAX_CLOCK_SOURCES 7
 
@@ -126,7 +130,18 @@ struct resource_funcs {
 			struct resource_context *res_ctx,
 			const struct resource_pool *pool,
 			struct dc_stream_state *stream);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+	void (*populate_dml_writeback_from_context)(
+			struct dc *dc,
+			struct resource_context *res_ctx,
+			display_e2e_pipe_params_st *pipes);
 
+	void (*set_mcif_arb_params)(
+			struct dc *dc,
+			struct dc_state *context,
+			display_e2e_pipe_params_st *pipes,
+			int pipe_cnt);
+#endif
 };
 
 struct audio_support{
@@ -154,6 +169,17 @@ struct resource_pool {
 	struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
 	bool i2c_hw_buffer_in_use;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+	struct dwbc *dwbc[MAX_DWB_PIPES];
+	struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
+	struct {
+		unsigned int gsl_0:1;
+		unsigned int gsl_1:1;
+		unsigned int gsl_2:1;
+	} gsl_groups;
+#endif
+
+
 	unsigned int pipe_count;
 	unsigned int underlay_pipe_index;
 	unsigned int stream_enc_count;
@@ -164,7 +190,11 @@ struct resource_pool {
 		unsigned int dchub_ref_clock_inKhz;
 	} ref_clocks;
 	unsigned int timing_generator_count;
+	unsigned int mpcc_count;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+	unsigned int writeback_pipe_count;
+#endif
 	/*
 	 * reserved clock source for DP
 	 */
@@ -201,6 +231,12 @@ struct stream_resource {
 	struct encoder_info_frame encoder_info_frame;
 
 	struct abm *abm;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+	/* There are only (num_pipes+1)/2 groups. 0 means unassigned,
+	 * otherwise it's using group number 'gsl_group-1'
+	 */
+	uint8_t gsl_group;
+#endif
 };
 
 struct plane_resource {
@@ -257,6 +293,10 @@ struct pipe_ctx {
 	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
 #endif
 	union pipe_update_flags update_flags;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+	struct dwbc *dwbc;
+	struct mcif_wb *mcif_wb;
+#endif
 };
 
 struct resource_context {
@@ -265,6 +305,9 @@ struct resource_context {
 	bool is_audio_acquired[MAX_PIPES];
 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
 	uint8_t dp_clock_source_ref_count;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+	bool is_dsc_acquired[MAX_PIPES];
+#endif
 };
 
 struct dce_bw_output {
@@ -284,9 +327,18 @@ struct dce_bw_output {
 	int blackout_recovery_time_us;
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dcn_bw_writeback {
+	struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
+};
+#endif
+
 struct dcn_bw_output {
 	struct dc_clocks clk;
 	struct dcn_watermark_set watermarks;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+	struct dcn_bw_writeback bw_writeback;
+#endif
 };
 
 union bw_output {

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DWBC_H__
+#define __DC_DWBC_H__
+
+#include "dc_hw_types.h"
+
+
+#define DWB_SW_V2	1
+#define DWB_MCIF_BUF_COUNT 4
+
+/* forward declaration of mcif_wb struct */
+struct mcif_wb;
+
+enum dce_version;
+
+enum dwb_sw_version {
+	dwb_ver_1_0 = 1,
+};
+
+enum dwb_source {
+	dwb_src_scl = 0,	/* for DCE7x/9x, DCN won't support. */
+	dwb_src_blnd,		/* for DCE7x/9x */
+	dwb_src_fmt,		/* for DCE7x/9x */
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+	dwb_src_otg0 = 0x100,	/* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
+	dwb_src_otg1,		/* for DCN1.x/DCN2.x */
+	dwb_src_otg2,		/* for DCN1.x/DCN2.x */
+	dwb_src_otg3,		/* for DCN1.x/DCN2.x */
+#else
+	dwb_src_otg0 = 0x100,	/* for DCN1.x, register: mmDWB_SOURCE_SELECT */
+	dwb_src_otg1,		/* for DCN1.x */
+	dwb_src_otg2,		/* for DCN1.x */
+	dwb_src_otg3,		/* for DCN1.x */
+#endif
+	dwb_src_mpc0 = 0x200,	/* for DCN2, register: mmMPC_DWB0_MUX, mmMPC_DWB1_MUX, mmMPC_DWB2_MUX */
+	dwb_src_mpc1,		/* for DCN2 */
+	dwb_src_mpc2,		/* for DCN2 */
+	dwb_src_mpc3,		/* for DCN2 */
+	dwb_src_mpc4,		/* for DCN2 */
+};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+/* DCN1.x, DCN2.x support 2 pipes */
+#else
+/* DCN1.x supports 2 pipes */
+#endif
+enum dwb_pipe {
+	dwb_pipe0 = 0,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+	dwb_pipe1,
+#endif
+	dwb_pipe_max_num,
+};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+enum dwb_frame_capture_enable {
+	DWB_FRAME_CAPTURE_DISABLE = 0,
+	DWB_FRAME_CAPTURE_ENABLE = 1,
+};
+
+enum dwb_stereo_eye_select {
+	DWB_STEREO_EYE_LEFT  = 1,		/* Capture left eye only */
+	DWB_STEREO_EYE_RIGHT = 2,		/* Capture right eye only */
+};
+
+enum dwb_stereo_type {
+	DWB_STEREO_TYPE_FRAME_PACKING = 0,		/* Frame packing */
+	DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3,	/* Frame sequential */
+};
+
+enum wbscl_coef_filter_type_sel {
+	WBSCL_COEF_LUMA_VERT_FILTER = 0,
+	WBSCL_COEF_CHROMA_VERT_FILTER = 1,
+	WBSCL_COEF_LUMA_HORZ_FILTER = 2,
+	WBSCL_COEF_CHROMA_HORZ_FILTER = 3
+};
+
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dwb_stereo_params {
+	bool				stereo_enabled;		/* false: normal mode, true: 3D stereo */
+	enum dwb_stereo_type		stereo_type;		/* indicates stereo format */
+	bool				stereo_polarity;	/* indicates left eye or right eye comes first in stereo mode */
+	enum dwb_stereo_eye_select	stereo_eye_select;	/* indicate which eye should be captured */
+};
+
+struct dwb_warmup_params {
+	bool	warmup_en;	/* false: normal mode, true: enable pattern generator */
+	bool	warmup_mode;	/* false: 420, true: 444 */
+	bool	warmup_depth;	/* false: 8bit, true: 10bit */
+	int	warmup_data;	/* Data to be sent by pattern generator (same for each pixel component) */
+	int	warmup_width;	/* Pattern width (pixels) */
+	int	warmup_height;	/* Pattern height (lines) */
+};
+#endif
+
+struct dwb_caps {
+	enum dce_version hw_version;	/* DCN engine version. */
+	enum dwb_sw_version sw_version;	/* DWB sw implementation version. */
+	unsigned int	reserved[6];	/* Reserved for future use, MUST BE 0. */
+	unsigned int	adapter_id;
+	unsigned int	num_pipes;	/* number of DWB pipes */
+	struct {
+		unsigned int support_dwb	:1;
+		unsigned int support_ogam	:1;
+		unsigned int support_wbscl	:1;
+		unsigned int support_ocsc	:1;
+	} caps;
+	unsigned int	 reserved2[10];	/* Reserved for future use, MUST BE 0. */
+};
+
+struct dwbc {
+	const struct dwbc_funcs *funcs;
+	struct dc_context *ctx;
+	int inst;
+	struct mcif_wb *mcif;
+	bool status;
+	int inputSrcSelect;
+	bool dwb_output_black;
+	enum dc_transfer_func_predefined tf;
+	enum dc_color_space output_color_space;
+};
+
+struct dwbc_funcs {
+	bool (*get_caps)(
+		struct dwbc *dwbc,
+		struct dwb_caps *caps);
+
+	bool (*enable)(
+		struct dwbc *dwbc,
+		struct dc_dwb_params *params);
+
+	bool (*disable)(struct dwbc *dwbc);
+
+	bool (*update)(
+		struct dwbc *dwbc,
+		struct dc_dwb_params *params);
+
+	bool (*is_enabled)(
+		struct dwbc *dwbc);
+
+	void (*set_stereo)(
+		struct dwbc *dwbc,
+		struct dwb_stereo_params *stereo_params);
+
+	void (*set_new_content)(
+		struct dwbc *dwbc,
+		bool is_new_content);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+	void (*set_warmup)(
+		struct dwbc *dwbc,
+		struct dwb_warmup_params *warmup_params);
+
+#endif
+
+	void (*dwb_set_scaler)(
+		struct dwbc *dwbc,
+		struct dc_dwb_params *params);
+};
+
+#endif

drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h

+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MCIF_WB_H__
+#define __DC_MCIF_WB_H__
+
+#include "dc_hw_types.h"
+
+
+enum mmhubbub_wbif_mode {
+	PACKED_444 = 0,
+	PACKED_444_FP16 = 1,
+	PLANAR_420_8BPC = 2,
+	PLANAR_420_10BPC = 3
+};
+
+struct mcif_arb_params {
+
+	unsigned int		time_per_pixel;
+	unsigned int		cli_watermark[4];
+	unsigned int		pstate_watermark[4];
+	unsigned int		arbitration_slice;
+	unsigned int		slice_lines;
+	unsigned int		max_scaled_time;
+};
+
+struct mcif_irq_params {
+	unsigned int		sw_int_en;
+	unsigned int		sw_slice_int_en;
+	unsigned int		sw_overrun_int_en;
+	unsigned int		vce_int_en;
+	unsigned int		vce_slice_int_en;
+};
+
+
+/* / - mcif_wb_frame_dump_info is the info of the dumping WB data */
+struct mcif_wb_frame_dump_info {
+	unsigned int		size;
+	unsigned int		width;
+	unsigned int		height;
+	unsigned int		luma_pitch;
+	unsigned int		chroma_pitch;
+	enum dwb_scaler_mode	format;
+};
+
+struct mcif_wb {
+	const struct mcif_wb_funcs *funcs;
+	struct dc_context *ctx;
+	int inst;
+};
+
+struct mcif_wb_funcs {
+
+	void (*enable_mcif)(struct mcif_wb *mcif_wb);
+
+	void (*disable_mcif)(struct mcif_wb *mcif_wb);
+
+	void (*config_mcif_buf)(
+		struct mcif_wb *mcif_wb,
+		struct mcif_buf_params *params,
+		unsigned int dest_height);
+
+	 void (*config_mcif_arb)(
+		struct mcif_wb *mcif_wb,
+		struct mcif_arb_params *params);
+
+	 void (*config_mcif_irq)(
+		struct mcif_wb *mcif_wb,
+		struct mcif_irq_params *params);
+
+	void (*dump_frame)(
+		struct mcif_wb *mcif_wb,
+		struct mcif_buf_params *mcif_params,
+		enum dwb_scaler_mode out_format,
+		unsigned int dest_width,
+		unsigned int dest_height,
+		struct mcif_wb_frame_dump_info *dump_info,
+		unsigned char *luma_buffer,
+		unsigned char *chroma_buffer,
+		unsigned char *dest_luma_buffer,
+		unsigned char *dest_chroma_buffer);
+};
+
+#endif