ARM: OMAP: Fix ASoC by enabling writes to XCCR and RCCR McBSP registers, v3

This patch enables writing to McBSP Transmit Configuration Control
Register (XCCR) and Receive Configuration Control Register (RCCR)
for 2430/34xx platforms. It also adds XCCR, RCCR entries in McBSP
register configuration structure and bit definitions for both
registers.

If we enable the writing to CCR registers for 2430/34xx and don't
set the default values (setting 0 as a consequence) in ASoC driver,
the Transmit/Receive DMA mode gets disabled and the the
transmission/reception doesn't happen, ending with a
"write error: Input/Output error" when playing with 'aplay'.

Also define dummy CCR registers for omap1.

Cc: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: NMisael Lopez Cruz <x0052729@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

arch/arm/plat-omap/include/mach/mcbsp.h

@@ -87,6 +87,10 @@
 #define OMAP_MCBSP_REG_XCERG	0x3A
 #define OMAP_MCBSP_REG_XCERH	0x3C
 
+/* Dummy defines, these are not available on omap1 */
+#define OMAP_MCBSP_REG_XCCR	0x00
+#define OMAP_MCBSP_REG_RCCR	0x00
+
 #define AUDIO_MCBSP_DATAWRITE	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
 
@@ -231,11 +235,16 @@
 #define XPBBLK(value)		((value)<<7)	/* Bits 7:8 */
 
 /*********************** McBSP XCCR bit definitions *************************/
+#define EXTCLKGATE		0x8000
+#define PPCONNECT		0x4000
+#define DXENDLY(value)		((value)<<12)	/* Bits 12:13 */
+#define XFULL_CYCLE		0x0800
 #define DILB			0x0020
 #define XDMAEN			0x0008
 #define XDISABLE		0x0001
 
 /********************** McBSP RCCR bit definitions *************************/
+#define RFULL_CYCLE		0x0800
 #define RDMAEN			0x0008
 #define RDISABLE		0x0001
 
@@ -267,6 +276,8 @@ struct omap_mcbsp_reg_cfg {
 	u16 rcerh;
 	u16 xcerg;
 	u16 xcerh;
+	u16 xccr;
+	u16 rccr;
 };
 
 typedef enum {

arch/arm/plat-omap/mcbsp.c

@@ -173,6 +173,10 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 	OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 	OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 	OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
+	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+		OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
+		OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
+	}
 }
 EXPORT_SYMBOL(omap_mcbsp_config);