drm/amdgpu/soc15: initialize reg base for vega12

Initialize the IP offsets for vega12.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/soc15.c

@@ -508,6 +508,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 	/* Set IP register base before any HW register access */
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
+	case CHIP_VEGA12:
 	case CHIP_RAVEN:
 		vega10_reg_base_init(adev);
 		break;