提交 30474544 编写于 作者: P Paul Walmsley 提交者: Kevin Hilman

ARM: OMAP3: PM: restrict erratum i443 handling to OMAP3430 only

Based on the documents that I have here, there doesn't appear to be an
equivalent to erratum i443 for OMAP3630, so restrict this one to OMAP34xx
chips.

Also, explicitly restrict this erratum to EMU and HS devices.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
上级 b02b9172
...@@ -407,13 +407,14 @@ void omap_sram_idle(void) ...@@ -407,13 +407,14 @@ void omap_sram_idle(void)
omap3_intc_prepare_idle(); omap3_intc_prepare_idle();
/* /*
* On EMU/HS devices ROM code restores a SRDC value * On EMU/HS devices ROM code restores a SRDC value
* from scratchpad which has automatic self refresh on timeout * from scratchpad which has automatic self refresh on timeout
* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
* Hence store/restore the SDRC_POWER register here. * Hence store/restore the SDRC_POWER register here.
*/ */
if (omap_rev() >= OMAP3430_REV_ES3_0 && if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
omap_type() != OMAP2_DEVICE_TYPE_GP && (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
core_next_state == PWRDM_POWER_OFF) core_next_state == PWRDM_POWER_OFF)
sdrc_pwr = sdrc_read_reg(SDRC_POWER); sdrc_pwr = sdrc_read_reg(SDRC_POWER);
...@@ -430,8 +431,9 @@ void omap_sram_idle(void) ...@@ -430,8 +431,9 @@ void omap_sram_idle(void)
omap34xx_do_sram_idle(save_state); omap34xx_do_sram_idle(save_state);
/* Restore normal SDRC POWER settings */ /* Restore normal SDRC POWER settings */
if (omap_rev() >= OMAP3430_REV_ES3_0 && if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
omap_type() != OMAP2_DEVICE_TYPE_GP && (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
core_next_state == PWRDM_POWER_OFF) core_next_state == PWRDM_POWER_OFF)
sdrc_write_reg(sdrc_pwr, SDRC_POWER); sdrc_write_reg(sdrc_pwr, SDRC_POWER);
......
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