提交 2d5a3c80 编写于 作者: T Tomi Valkeinen

arm: dra7: add DESHDCP clock

Add a new Linux clock for DRA7 based SoCs to control DESHDCP clock.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
上级 c65b99f0
......@@ -131,6 +131,11 @@
regulator-max-microvolt = <3000000>;
};
};
scm_conf_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
dra7_pmx_core: pinmux@1400 {
......
......@@ -2136,3 +2136,13 @@
clocks = <&dpll_usb_ck>;
};
};
&scm_conf_clocks {
dss_deshdcp_clk: dss_deshdcp_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
};
......@@ -438,6 +438,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "video2_clk", .clk = "dss_video2_clk" },
{ .role = "video1_clk", .clk = "dss_video1_clk" },
{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
{ .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
};
static struct omap_hwmod dra7xx_dss_hwmod = {
......
......@@ -305,6 +305,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
{ .node_name = NULL },
};
......
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