Revert "net: hns3: disbable pfc en before the reset"

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7S5M4
CVE: NA

----------------------------------------------------------------------

This reverts commit 29e4bb1a.
Signed-off-by: NJiantao Xiao <xiaojiantao1@h-partners.com>

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c

@@ -6,7 +6,6 @@
 #include "hnae3_ext.h"
 #include "hclge_cmd.h"
 #include "hclge_ext.h"
-#include "hclge_tm.h"
 
 static nic_event_fn_t nic_event_call;
 
@@ -1449,7 +1448,6 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
 	[HNAE3_EXT_OPC_DISABLE_LANE] = hclge_disable_net_lane,
 	[HNAE3_EXT_OPC_GET_LANE_STATUS] = hclge_get_net_lane_status,
 	[HNAE3_EXT_OPC_DISABLE_CLOCK] = hclge_disable_nic_clock,
-	[HNAE3_EXT_OPC_SET_PFC_TIME] = hclge_set_pause_trans_time,
 	[HNAE3_EXT_OPC_GET_HILINK_REF_LOS] = hclge_get_hilink_ref_los,
 	[HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS] = hclge_get_port_fault_status,
 	[HNAE3_EXT_OPC_GET_PORT_TYPE] = hclge_get_port_wire_type,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

@@ -8486,15 +8486,12 @@ static void hclge_ae_stop(struct hnae3_handle *handle)
 	/* If it is not PF reset or FLR, the firmware will disable the MAC,
 	 * so it only need to stop phy here.
 	 */
-	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
-		hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
-				       HCLGE_PFC_DISABLE);
-		if (hdev->reset_type != HNAE3_FUNC_RESET &&
-		    hdev->reset_type != HNAE3_FLR_RESET) {
-			hclge_mac_stop_phy(hdev);
-			hclge_update_link_status(hdev);
-			return;
-		}
+	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
+	    hdev->reset_type != HNAE3_FUNC_RESET &&
+	    hdev->reset_type != HNAE3_FLR_RESET) {
+		hclge_mac_stop_phy(hdev);
+		hclge_update_link_status(hdev);
+		return;
 	}
 
 	hclge_reset_tqp(handle);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

@@ -171,8 +171,8 @@ int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
 	return hclge_cmd_send(&hdev->hw, &desc, 1);
 }
 
-int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
-			   u8 pfc_bitmap)
+static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
+				  u8 pfc_bitmap)
 {
 	struct hclge_desc desc;
 	struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

@@ -167,9 +167,6 @@ struct hclge_bp_to_qs_map_cmd {
 	u32 rsvd1;
 };
 
-#define HCLGE_PFC_DISABLE	0
-#define HCLGE_PFC_TX_RX_DISABLE	0
-
 struct hclge_pfc_en_cmd {
 	u8 tx_rx_en_bitmap;
 	u8 pri_en_bitmap;
@@ -242,8 +239,6 @@ void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
-int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
-			   u8 pfc_bitmap);
 int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
 			  u8 pause_trans_gap, u16 pause_trans_time);
 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);