x86/traps: Demand-populate PASID MSR via #GP
mainline inclusion from mainline-v5.18 commit fa6af69f category: feature bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I596WO CVE: NA Intel-SIG: commit fa6af69f x86/traps: Demand-populate PASID MSR via #GP. Incremental backporting patches for DSA/IAA on Intel Xeon platform. -------------------------------- All tasks start with PASID state disabled. This means that the first time they execute an ENQCMD instruction they will take a #GP fault. Modify the #GP fault handler to check if the "mm" for the task has already been allocated a PASID. If so, try to fix the #GP fault by loading the IA32_PASID MSR. Signed-off-by: NFenghua Yu <fenghua.yu@intel.com> Signed-off-by: NBorislav Petkov <bp@suse.de> Reviewed-by: NTony Luck <tony.luck@intel.com> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20220207230254.3342514-9-fenghua.yu@intel.comSigned-off-by: NXiaochen Shen <xiaochen.shen@intel.com>
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