mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE

This controller only does ECC on full-page accesses, even though the
ECC consists of multiple steps.  fsl_elbc_nand can get away with this
because the ECC of an all-0xff region will be all-0xff, but this is not
true with the ECC algorithms used by IFC.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

drivers/mtd/nand/fsl_ifc_nand.c

@@ -823,7 +823,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 
 	/* set up nand options */
 	chip->bbt_options = NAND_BBT_USE_FLASH;
-
+	chip->options = NAND_NO_SUBPAGE_WRITE;
 
 	if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
 		chip->read_byte = fsl_ifc_read_byte16;