提交 1bc9f40a 编写于 作者: K Krzysztof Kozlowski 提交者: Zheng Zengkai

memory: samsung: exynos5422-dmc: handle clk_set_parent() failure

stable inclusion
from stable-5.10.37
commit 7bb63ed88189a55d1d618264dafbe37a1f285b56
bugzilla: 51868
CVE: NA

--------------------------------

[ Upstream commit 132c17c3 ]

clk_set_parent() can fail and ignoring such case could lead to invalid
clock setup for given frequency.

Addresses-Coverity: Unchecked return value
Fixes: 6e7674c3 ("memory: Add DMC driver for Exynos5422")
Signed-off-by: NKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: NLukasz Luba <lukasz.luba@arm.com>
Link: https://lore.kernel.org/r/20210407154535.70756-1-krzysztof.kozlowski@canonical.comSigned-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Acked-by: NWeilong Chen <chenweilong@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
上级 7c7f8674
...@@ -1298,7 +1298,9 @@ static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc) ...@@ -1298,7 +1298,9 @@ static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
dmc->curr_volt = target_volt; dmc->curr_volt = target_volt;
clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); ret = clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
if (ret)
return ret;
clk_prepare_enable(dmc->fout_bpll); clk_prepare_enable(dmc->fout_bpll);
clk_prepare_enable(dmc->mout_bpll); clk_prepare_enable(dmc->mout_bpll);
......
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