[PATCH] m32r: Update syscall macros for MMU-less targets
This patch is for updating m32r's MMU-less support. Some legacy MMU-less m32r chips cannot return from a trap handler to the right-hand side 16-bit halfword code of a 32-bit instrucion code pair, because a "trap" instruction specification was expanded in M32R-II ISA. This modification forces "trap" instructions to be placed in word alignment location with a parallel "nop" code. Signed-off-by: NKazuhiro Inaoka <inaoka@linux-m32r.org> Signed-off-by: NHirokazu Takata <takata@linux-m32r.org> Signed-off-by: NAndrew Morton <akpm@osdl.org> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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