提交 170ee4d7 编写于 作者: L Linus Torvalds

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "Two fixes for the new SM8150 and SM8250 Qualcomm clk drivers to fix a
  randconfig build error and an incorrect parent mapping"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: gcc: Fix parent for gpll0_out_even
  clk: qcom: sm8250 gcc depends on QCOM_GDSC
...@@ -377,6 +377,7 @@ config SM_GCC_8150 ...@@ -377,6 +377,7 @@ config SM_GCC_8150
config SM_GCC_8250 config SM_GCC_8250
tristate "SM8250 Global Clock Controller" tristate "SM8250 Global Clock Controller"
select QCOM_GDSC
help help
Support for the global clock controller on SM8250 devices. Support for the global clock controller on SM8250 devices.
Say Y if you want to use peripheral devices such as UART, Say Y if you want to use peripheral devices such as UART,
......
...@@ -76,8 +76,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { ...@@ -76,8 +76,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even", .name = "gpll0_out_even",
.parent_data = &(const struct clk_parent_data){ .parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .hw = &gpll0.clkr.hw,
.name = "bi_tcxo",
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_trion_pll_postdiv_ops, .ops = &clk_trion_pll_postdiv_ops,
......
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