提交 157cc5aa 编写于 作者: M Michael Hennerich 提交者: Bryan Wu

Blackfin arch: Disable CACHELINE_ALIGNED_L1 for BF54x by default

Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>
上级 f40d24d9
...@@ -540,7 +540,8 @@ config IP_CHECKSUM_L1 ...@@ -540,7 +540,8 @@ config IP_CHECKSUM_L1
config CACHELINE_ALIGNED_L1 config CACHELINE_ALIGNED_L1
bool "Locate cacheline_aligned data to L1 Data Memory" bool "Locate cacheline_aligned data to L1 Data Memory"
default y default y if !BF54x
default n if BF54x
depends on !BF531 depends on !BF531
help help
If enabled cacheline_anligned data is linked If enabled cacheline_anligned data is linked
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册