net/mlx5e: Fix setting of RS FEC mode
stable inclusion from stable-5.10.32 commit e072247938a8551187f1ad3f9f928d968c96fd0c bugzilla: 51796 -------------------------------- commit 7a320c9d upstream. Change register setting from bit number to bit mask. Fixes: b5ede32d ("net/mlx5e: Add support for FEC modes based on 50G per lane links") Signed-off-by: NAya Levin <ayal@nvidia.com> Reviewed-by: NEran Ben Elisha <eranbe@nvidia.com> Signed-off-by: NSaeed Mahameed <saeedm@nvidia.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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