提交 0e44ba77 编写于 作者: T Thomas Gleixner 提交者: Lin Wang

x86/fpu: Convert tracing to fpstate

mainline inclusion
from mainline-v5.16-rc1
commit cceb4964
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I590ZC
CVE: NA

Intel-SIG: commit cceb4964 x86/fpu: Convert tracing to fpstate.

--------------------------------

Convert FPU tracing code to the new register storage mechanism in
preparation for dynamically sized buffers.

No functional change.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20211013145322.503327333@linutronix.deSigned-off-by: NLin Wang <lin.x.wang@intel.com>
上级 f07a6bc9
...@@ -22,8 +22,8 @@ DECLARE_EVENT_CLASS(x86_fpu, ...@@ -22,8 +22,8 @@ DECLARE_EVENT_CLASS(x86_fpu,
__entry->fpu = fpu; __entry->fpu = fpu;
__entry->load_fpu = test_thread_flag(TIF_NEED_FPU_LOAD); __entry->load_fpu = test_thread_flag(TIF_NEED_FPU_LOAD);
if (boot_cpu_has(X86_FEATURE_OSXSAVE)) { if (boot_cpu_has(X86_FEATURE_OSXSAVE)) {
__entry->xfeatures = fpu->state.xsave.header.xfeatures; __entry->xfeatures = fpu->fpstate->regs.xsave.header.xfeatures;
__entry->xcomp_bv = fpu->state.xsave.header.xcomp_bv; __entry->xcomp_bv = fpu->fpstate->regs.xsave.header.xcomp_bv;
} }
), ),
TP_printk("x86/fpu: %p load: %d xfeatures: %llx xcomp_bv: %llx", TP_printk("x86/fpu: %p load: %d xfeatures: %llx xcomp_bv: %llx",
......
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