arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent

stable inclusion
from stable-5.10.43
commit d866a6e61a4de0eb13973eb8a85c780323876711
bugzilla: 109284
CVE: NA

--------------------------------

[ Upstream commit 52ae30f5 ]

Traffic through main NAVSS interconnect is coherent wrt ARM caches on
J7200 SoC.  Add missing dma-coherent property to main_navss node.

Also add dma-ranges to be consistent with mcu_navss node
and with AM65/J721e main_navss and mcu_navss nodes.

Fixes: d361ed88 ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NPeter Ujfalusi <peter.ujfalusi@gmail.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210510180601.19458-1-vigneshr@ti.comSigned-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

@@ -78,6 +78,8 @@
 		#size-cells = <2>;
 		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 		ti,sci-dev-id = <199>;
+		dma-coherent;
+		dma-ranges;
 
 		main_navss_intr: interrupt-controller1 {
 			compatible = "ti,sci-intr";