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提交 07500138 编写于 作者: M Maxime Jourdan 提交者： Neil Armstrong
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clk: meson: axg-audio: add g12a support 

The g12a audio clock controller is largely similar to the existing axg
controller, with the addition of the spdif output B and TDM pad clocks.

This commit extends the existing axg audio clock controller driver
to work with multiple compatibles and add the g12a specific clocks
Signed-off-by: NMaxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190329160649.31603-5-jbrunet@baylibre.com
上级 6d6d2a24
隐藏空白更改
内联 并排
Showing with 239 addition and 8 deletion
drivers/clk/meson/axg-audio.c
浏览文件 @ 07500138
......@@ -97,6 +97,7 @@ static AUD_PCLK_GATE(spdifin, 16);
static AUD_PCLK_GATE(spdifout, 17);
static AUD_PCLK_GATE(resample, 18);
static AUD_PCLK_GATE(power_detect, 19);
static AUD_PCLK_GATE(spdifout_b, 21);
/* Audio Master Clocks */
static const char * const mst_mux_parent_names[] = {
......@@ -124,6 +125,7 @@ static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
static AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
static AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
static AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
#define AUD_MST_DIV(_name, _reg, _flag) \
AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
......@@ -145,6 +147,7 @@ static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
static AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
static AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
#define AUD_MST_MCLK_GATE(_name, _reg) \
AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \
......@@ -160,6 +163,7 @@ static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
static AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
static AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
static AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
/* Sample Clocks */
#define AUD_MST_SCLK_PRE_EN(_name, _reg) \
......@@ -377,6 +381,45 @@ static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
/* G12a Pad control */
#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \
AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \
CLK_SET_RATE_NO_REPARENT)
static const char * const mclk_pad_ctrl_parent_names[] = {
"aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk",
"aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk",
};
static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
mclk_pad_ctrl_parent_names);
static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
mclk_pad_ctrl_parent_names);
static const char * const lrclk_pad_ctrl_parent_names[] = {
"aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
"aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
};
static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
lrclk_pad_ctrl_parent_names);
static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
lrclk_pad_ctrl_parent_names);
static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
lrclk_pad_ctrl_parent_names);
static const char * const sclk_pad_ctrl_parent_names[] = {
"aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
"aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
};
static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
sclk_pad_ctrl_parent_names);
static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
sclk_pad_ctrl_parent_names);
static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
sclk_pad_ctrl_parent_names);
/*
* Array of all clocks provided by this provider
* The input clocks of the controller will be populated at runtime
......@@ -509,7 +552,156 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
.num = NR_CLKS,
};
/* Convenience table to populate regmap in .probe() */
/*
* Array of all G12A clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
.hws = {
[AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
[AUD_CLKID_PDM] = &aud_pdm.hw,
[AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
[AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
[AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw,
[AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
[AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
[AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
[AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw,
[AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
[AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
[AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw,
[AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
[AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
[AUD_CLKID_TODDR_C] = &aud_toddr_c.hw,
[AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
[AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
[AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw,
[AUD_CLKID_RESAMPLE] = &aud_resample.hw,
[AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw,
[AUD_CLKID_SPDIFOUT_B] = &aud_spdifout_b.hw,
[AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw,
[AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw,
[AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw,
[AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw,
[AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw,
[AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw,
[AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
[AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
[AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
[AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
[AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw,
[AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw,
[AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
[AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
[AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
[AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
[AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw,
[AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw,
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw,
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw,
[AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw,
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &aud_spdifout_b_clk_sel.hw,
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &aud_spdifout_b_clk_div.hw,
[AUD_CLKID_SPDIFOUT_B_CLK] = &aud_spdifout_b_clk.hw,
[AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw,
[AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
[AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
[AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw,
[AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw,
[AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw,
[AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw,
[AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw,
[AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw,
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw,
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw,
[AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
[AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
[AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
[AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
[AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw,
[AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw,
[AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
[AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
[AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
[AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
[AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw,
[AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw,
[AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
[AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
[AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
[AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
[AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw,
[AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw,
[AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
[AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
[AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
[AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
[AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw,
[AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw,
[AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
[AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
[AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
[AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
[AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw,
[AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw,
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw,
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw,
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw,
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw,
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw,
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw,
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw,
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
[AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
[AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
[AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw,
[AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
[AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
[AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
[AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw,
[AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
[AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
[AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw,
[AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
[AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
[AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
[AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw,
[AUD_CLKID_TDM_MCLK_PAD0] = &aud_tdm_mclk_pad_0.hw,
[AUD_CLKID_TDM_MCLK_PAD1] = &aud_tdm_mclk_pad_1.hw,
[AUD_CLKID_TDM_LRCLK_PAD0] = &aud_tdm_lrclk_pad_0.hw,
[AUD_CLKID_TDM_LRCLK_PAD1] = &aud_tdm_lrclk_pad_1.hw,
[AUD_CLKID_TDM_LRCLK_PAD2] = &aud_tdm_lrclk_pad_2.hw,
[AUD_CLKID_TDM_SCLK_PAD0] = &aud_tdm_sclk_pad_0.hw,
[AUD_CLKID_TDM_SCLK_PAD1] = &aud_tdm_sclk_pad_1.hw,
[AUD_CLKID_TDM_SCLK_PAD2] = &aud_tdm_sclk_pad_2.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
};
/* Convenience table to populate regmap in .probe()
* Note that this table is shared between both AXG and G12A,
* with spdifout_b clocks being exclusive to G12A. Since those
* clocks are not declared within the AXG onecell table, we do not
* feel the need to have separate AXG/G12A regmap tables.
*/
static struct clk_regmap *const aud_clk_regmaps[] = {
&aud_ddr_arb,
&aud_pdm,
......@@ -531,6 +723,7 @@ static struct clk_regmap *const aud_clk_regmaps[] = {
&aud_spdifout,
&aud_resample,
&aud_power_detect,
&aud_spdifout_b,
&aud_mst_a_mclk_sel,
&aud_mst_b_mclk_sel,
&aud_mst_c_mclk_sel,
......@@ -632,6 +825,17 @@ static struct clk_regmap *const aud_clk_regmaps[] = {
&aud_tdmout_a_lrclk,
&aud_tdmout_b_lrclk,
&aud_tdmout_c_lrclk,
&aud_spdifout_b_clk_sel,
&aud_spdifout_b_clk_div,
&aud_spdifout_b_clk,
&aud_tdm_mclk_pad_0,
&aud_tdm_mclk_pad_1,
&aud_tdm_lrclk_pad_0,
&aud_tdm_lrclk_pad_1,
&aud_tdm_lrclk_pad_2,
&aud_tdm_sclk_pad_0,
&aud_tdm_sclk_pad_1,
&aud_tdm_sclk_pad_2,
};
static int devm_clk_get_enable(struct device *dev, char *id)
......@@ -719,15 +923,24 @@ static const struct regmap_config axg_audio_regmap_cfg = {
.max_register = AUDIO_CLK_PDMIN_CTRL1,
};
struct audioclk_data {
struct clk_hw_onecell_data *hw_onecell_data;
};
static int axg_audio_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct audioclk_data *data;
struct regmap *map;
struct resource *res;
void __iomem *regs;
struct clk_hw *hw;
int ret, i;
data = of_device_get_match_data(dev);
if (!data)
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs))
......@@ -778,8 +991,8 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
aud_clk_regmaps[i]->map = map;
/* Take care to skip the registered input clocks */
for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {
hw = axg_audio_hw_onecell_data.hws[i];
for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
hw = data->hw_onecell_data->hws[i];
/* array might be sparse */
if (!hw)
continue;
......@@ -793,12 +1006,25 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
&axg_audio_hw_onecell_data);
data->hw_onecell_data);
}
static const struct audioclk_data axg_audioclk_data = {
.hw_onecell_data = &axg_audio_hw_onecell_data,
};
static const struct audioclk_data g12a_audioclk_data = {
.hw_onecell_data = &g12a_audio_hw_onecell_data,
};
static const struct of_device_id clkc_match_table[] = {
{ .compatible = "amlogic,axg-audio-clkc" },
{}
{
.compatible = "amlogic,axg-audio-clkc",
.data = &axg_audioclk_data
}, {
.compatible = "amlogic,g12a-audio-clkc",
.data = &g12a_audioclk_data
}, {}
};
MODULE_DEVICE_TABLE(of, clkc_match_table);
......@@ -811,6 +1037,6 @@ static struct platform_driver axg_audio_driver = {
};
module_platform_driver(axg_audio_driver);
MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver");
MODULE_DESCRIPTION("Amlogic AXG/G12A Audio Clock driver");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
drivers/clk/meson/axg-audio.h
浏览文件 @ 07500138
......@@ -20,6 +20,8 @@
#define AUDIO_MCLK_D_CTRL 0x010
#define AUDIO_MCLK_E_CTRL 0x014
#define AUDIO_MCLK_F_CTRL 0x018
#define AUDIO_MST_PAD_CTRL0 0x01c
#define AUDIO_MST_PAD_CTRL1 0x020
#define AUDIO_MST_A_SCLK_CTRL0 0x040
#define AUDIO_MST_A_SCLK_CTRL1 0x044
#define AUDIO_MST_B_SCLK_CTRL0 0x048
......@@ -45,6 +47,7 @@
#define AUDIO_CLK_LOCKER_CTRL 0x0A8
#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
/*
* CLKID index values
......@@ -109,10 +112,12 @@
#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
/* include the CLKIDs which are part of the DT bindings */
#include <dt-bindings/clock/axg-audio-clkc.h>
#define NR_CLKS 151
#define NR_CLKS 163
#endif /*__AXG_AUDIO_CLKC_H */
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