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提交 0651dfab 编写于 作者: D Deepak Rawat 提交者： Roland Scheidegger
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drm/vmwgfx: Sync virtual device headers for new feature 

Get the latest device headers for SM5 and other features development.

v2: sync to newer bits (merge later commits)
v3: sync to even newer bits
Co-developed-by: NRoland Scheidegger <sroland@vmware.com>
Signed-off-by: NDeepak Rawat <drawat.floss@gmail.com>
Signed-off-by: NNeha Bhende <bhenden@vmware.com>
Signed-off-by: NCharmaine Lee <charmainel@vmware.com>
Signed-off-by: NRoland Scheidegger <sroland@vmware.com>
Reviewed-by: NThomas Hellström (VMware) <thomas_os@shipmail.org>
上级 878c6ecd
展开全部 隐藏空白更改
内联 并排
Showing with 1646 addition and 585 deletion
drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
浏览文件 @ 0651dfab
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 1998-2015 VMware, Inc.
* Copyright 1998-2020 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
......@@ -261,30 +261,23 @@ typedef enum {
SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
/*
* Reserve some IDs to be used for the SM5 shader types.
*/
SVGA_3D_CMD_DX_RESERVED1 = 1223,
SVGA_3D_CMD_DX_RESERVED2 = 1224,
SVGA_3D_CMD_DX_RESERVED3 = 1225,
SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223,
SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224,
SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225,
SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
SVGA_3D_CMD_DX_MAX = 1227,
SVGA_3D_CMD_SCREEN_COPY = 1227,
/*
* Reserve some IDs to be used for video.
*/
SVGA_3D_CMD_VIDEO_RESERVED1 = 1228,
SVGA_3D_CMD_VIDEO_RESERVED2 = 1229,
SVGA_3D_CMD_VIDEO_RESERVED3 = 1230,
SVGA_3D_CMD_VIDEO_RESERVED4 = 1231,
SVGA_3D_CMD_VIDEO_RESERVED5 = 1232,
SVGA_3D_CMD_VIDEO_RESERVED6 = 1233,
SVGA_3D_CMD_VIDEO_RESERVED7 = 1234,
SVGA_3D_CMD_VIDEO_RESERVED8 = 1235,
SVGA_3D_CMD_RESERVED1 = 1228,
SVGA_3D_CMD_RESERVED2 = 1229,
SVGA_3D_CMD_RESERVED3 = 1230,
SVGA_3D_CMD_RESERVED4 = 1231,
SVGA_3D_CMD_RESERVED5 = 1232,
SVGA_3D_CMD_RESERVED6 = 1233,
SVGA_3D_CMD_RESERVED7 = 1234,
SVGA_3D_CMD_RESERVED8 = 1235,
SVGA_3D_CMD_GROW_OTABLE = 1236,
SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
......@@ -298,7 +291,46 @@ typedef enum {
SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,
SVGA_3D_CMD_MAX = 1245,
SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245,
SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246,
SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247,
SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248,
SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249,
SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250,
SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251,
SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252,
SVGA_3D_CMD_DX_DISPATCH = 1253,
SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254,
SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255,
SVGA_3D_CMD_HINT_ZERO_SURFACE = 1256,
SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257,
SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258,
SVGA_3D_CMD_LOGICOPS_BITBLT = 1259,
SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260,
SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261,
SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262,
SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263,
SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264,
SVGA_3D_CMD_RESERVED2_1 = 1265,
SVGA_3D_CMD_RESERVED2_2 = 1266,
SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267,
SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268,
SVGA_3D_CMD_DX_SET_MIN_LOD = 1269,
SVGA_3D_CMD_RESERVED2_3 = 1270,
SVGA_3D_CMD_RESERVED2_4 = 1271,
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272,
SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273,
SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274,
SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275,
SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276,
SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277,
SVGA_3D_CMD_MAX = 1278,
SVGA_3D_CMD_FUTURE_MAX = 3000
} SVGAFifo3dCmdId;
......@@ -334,6 +366,7 @@ struct {
uint32 sid;
SVGA3dSurface1Flags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
......@@ -341,6 +374,7 @@ struct {
* numMipLevels set to 0.
*/
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
......@@ -360,6 +394,7 @@ struct {
uint32 sid;
SVGA3dSurface1Flags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
......@@ -369,6 +404,7 @@ struct {
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
......@@ -512,6 +548,18 @@ struct {
#include "vmware_pack_end.h"
SVGA3dCmdWholeSurfaceCopy; /* SVGA_3D_CMD_WHOLE_SURFACE_COPY */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dest;
SVGA3dBox boxSrc;
SVGA3dBox boxDest;
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceStretchBltNonMSToMS;
/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS */
typedef
#include "vmware_pack_begin.h"
struct {
......@@ -555,6 +603,7 @@ struct {
SVGAGuestImage guest;
SVGA3dSurfaceImageId host;
SVGA3dTransferType transfer;
/*
* Followed by variable number of SVGA3dCopyBox structures. For consistency
* in all clipping logic and coordinate translation, we define the
......@@ -789,7 +838,7 @@ struct {
uint32 indexBufferSid; /* Valid index buffer sid. */
uint32 indexBufferOffset; /* Byte offset into the vertex buffer, almost */
/* always 0 for DX9 guests, non-zero for OpenGL */
/* always 0 for pre SM guests, non-zero for OpenGL */
/* guests. We can't represent non-multiple of */
/* stride offsets in D3D9Renderer... */
uint8 indexBufferStride; /* Allowable values = 1, 2, or 4 */
......@@ -1228,6 +1277,7 @@ struct SVGA3dCmdLogicOpsBitBlt {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
SVGA3dLogicOp logicOp;
SVGA3dLogicOpRop3 logicOpRop3;
/* Followed by variable number of SVGA3dCopyBox structures */
}
#include "vmware_pack_end.h"
......@@ -1247,7 +1297,8 @@ struct SVGA3dCmdLogicOpsTransBlt {
uint32 color;
uint32 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
SVGA3dSignedBox dstBox;
SVGA3dBox clipBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */
......@@ -1266,7 +1317,8 @@ struct SVGA3dCmdLogicOpsStretchBlt {
uint16 mode;
uint16 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
SVGA3dSignedBox dstBox;
SVGA3dBox clipBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
......@@ -1283,6 +1335,7 @@ struct SVGA3dCmdLogicOpsColorFill {
SVGA3dSurfaceImageId dst;
uint32 color;
SVGA3dLogicOp logicOp;
SVGA3dLogicOpRop3 logicOpRop3;
/* Followed by variable number of SVGA3dRect structures. */
}
#include "vmware_pack_end.h"
......@@ -1302,7 +1355,8 @@ struct SVGA3dCmdLogicOpsAlphaBlend {
uint32 alphaVal;
uint32 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
SVGA3dSignedBox dstBox;
SVGA3dBox clipBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
......@@ -1365,8 +1419,9 @@ struct {
SVGA3dSurface2Flags surface2Flags;
uint8 multisamplePattern;
uint8 qualityLevel;
uint8 pad0[2];
uint32 pad1[3];
uint16 bufferByteStride;
float minLOD;
uint32 pad0[2];
}
#include "vmware_pack_end.h"
SVGAOTableSurfaceEntry;
......@@ -1543,7 +1598,7 @@ typedef
#include "vmware_pack_begin.h"
struct {
SVGAOTableType type;
PPN baseAddress;
PPN32 baseAddress;
uint32 sizeInBytes;
uint32 validSizeInBytes;
SVGAMobFormat ptDepth;
......@@ -1599,7 +1654,7 @@ typedef
struct SVGA3dCmdDefineGBMob {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN base;
PPN32 base;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
......@@ -1618,7 +1673,6 @@ struct SVGA3dCmdDestroyGBMob {
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
/*
* Define a memory object (Mob) in the OTable with a PPN64 base.
*/
......@@ -1718,6 +1772,27 @@ struct SVGA3dCmdDefineGBSurface_v3 {
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBSurface_v3; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 */
/*
* Defines a guest-backed surface, adding buffer byte stride.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBSurface_v4 {
uint32 sid;
SVGA3dSurfaceAllFlags surfaceFlags;
SVGA3dSurfaceFormat format;
uint32 numMipLevels;
uint32 multisampleCount;
SVGA3dMSPattern multisamplePattern;
SVGA3dMSQualityLevel qualityLevel;
SVGA3dTextureFilter autogenFilter;
SVGA3dSize size;
uint32 arraySize;
uint32 bufferByteStride;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBSurface_v4; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 */
/*
* Destroy a guest-backed surface.
*/
......@@ -2181,4 +2256,20 @@ SVGA3dCmdScreenCopy; /* SVGA_3D_CMD_SCREEN_COPY */
#define SVGA_SCREEN_COPY_STATUS_SUCCESS 0x01
#define SVGA_SCREEN_COPY_STATUS_INVALID 0xFFFFFFFF
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdWriteZeroSurface; /* SVGA_3D_CMD_WRITE_ZERO_SURFACE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdHintZeroSurface; /* SVGA_3D_CMD_HINT_ZERO_SURFACE */
#endif /* _SVGA3D_CMD_H_ */
drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
浏览文件 @ 0651dfab
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 2012-2015 VMware, Inc.
* Copyright 2012-2019 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
......@@ -118,12 +118,14 @@ typedef uint8 SVGA3dMultisampleRastEnable;
#define SVGA3D_DX_MAX_SRVIEWS 128
#define SVGA3D_DX_MAX_CONSTBUFFERS 16
#define SVGA3D_DX_MAX_SAMPLERS 16
#define SVGA3D_DX_MAX_CLASS_INSTANCES 253
#define SVGA3D_DX_MAX_CONSTBUF_BINDING_SIZE (4096 * 4 * (uint32)sizeof(uint32))
typedef uint32 SVGA3dShaderResourceViewId;
typedef uint32 SVGA3dRenderTargetViewId;
typedef uint32 SVGA3dDepthStencilViewId;
typedef uint32 SVGA3dUAViewId;
typedef uint32 SVGA3dShaderId;
typedef uint32 SVGA3dElementLayoutId;
......@@ -145,6 +147,17 @@ typedef union {
float value[4];
} SVGA3dRGBAFloat;
typedef union {
struct {
uint32 r;
uint32 g;
uint32 b;
uint32 a;
};
uint32 value[4];
} SVGA3dRGBAUint32;
typedef
#include "vmware_pack_begin.h"
struct {
......@@ -249,6 +262,39 @@ struct SVGA3dCmdDXSetShader {
#include "vmware_pack_end.h"
SVGA3dCmdDXSetShader; /* SVGA_3D_CMD_DX_SET_SHADER */
typedef union {
struct {
uint32 cbOffset : 12;
uint32 cbId : 4;
uint32 baseSamp : 4;
uint32 baseTex : 7;
uint32 reserved : 5;
};
uint32 value;
} SVGA3dIfaceData;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetShaderIface {
SVGA3dShaderType type;
uint32 numClassInstances;
uint32 index;
uint32 iface;
SVGA3dIfaceData data;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetShaderIface; /* SVGA_3D_CMD_DX_SET_SHADER_IFACE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBindShaderIface {
uint32 cid;
SVGAMobId mobid;
uint32 offsetInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBindShaderIface; /* SVGA_3D_CMD_DX_BIND_SHADER_IFACE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetSamplers {
......@@ -304,6 +350,26 @@ struct SVGA3dCmdDXDrawIndexedInstanced {
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawIndexedInstanced; /* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDrawIndexedInstancedIndirect {
SVGA3dSurfaceId argsBufferSid;
uint32 byteOffsetForArgs;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawIndexedInstancedIndirect;
/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDrawInstancedIndirect {
SVGA3dSurfaceId argsBufferSid;
uint32 byteOffsetForArgs;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawInstancedIndirect;
/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDrawAuto {
......@@ -312,6 +378,27 @@ struct SVGA3dCmdDXDrawAuto {
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawAuto; /* SVGA_3D_CMD_DX_DRAW_AUTO */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDispatch {
uint32 threadGroupCountX;
uint32 threadGroupCountY;
uint32 threadGroupCountZ;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDispatch;
/* SVGA_3D_CMD_DX_DISPATCH */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDispatchIndirect {
SVGA3dSurfaceId argsBufferSid;
uint32 byteOffsetForArgs;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDispatchIndirect;
/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetInputLayout {
......@@ -525,7 +612,7 @@ struct MKS3dDXSOState {
uint32 offset; /* Starting offset */
uint32 intOffset; /* Internal offset */
uint32 vertexCount; /* vertices written */
uint32 sizeInBytes; /* max bytes to write */
uint32 dead;
}
#include "vmware_pack_end.h"
SVGA3dDXSOState;
......@@ -786,6 +873,31 @@ struct SVGA3dCmdDXTransferFromBuffer {
SVGA3dCmdDXTransferFromBuffer; /* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER */
#define SVGA3D_TRANSFER_TO_BUFFER_READBACK (1 << 0)
#define SVGA3D_TRANSFER_TO_BUFFER_FLAGS_MASK (1 << 0)
typedef uint32 SVGA3dTransferToBufferFlags;
/*
* Raw byte wise transfer to a buffer surface from another surface
* of the requested box. Supported if SVGA_CAP_DX2 is set. This
* command does not take a context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXTransferToBuffer {
SVGA3dSurfaceId srcSid;
uint32 srcSubResource;
SVGA3dBox srcBox;
SVGA3dSurfaceId destSid;
uint32 destOffset;
uint32 destPitch;
uint32 destSlicePitch;
SVGA3dTransferToBufferFlags flags;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXTransferToBuffer; /* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER */
/*
* Raw byte wise transfer from a buffer surface into another surface
* of the requested box. Supported if SVGA3D_DEVCAP_DXCONTEXT is set.
......@@ -905,6 +1017,20 @@ typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetPSConstantBufferOffset;
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetGSConstantBufferOffset;
/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetHSConstantBufferOffset;
/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetDSConstantBufferOffset;
/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetCSConstantBufferOffset;
/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET */
#define SVGA3D_BUFFEREX_SRV_RAW (1 << 0)
#define SVGA3D_BUFFEREX_SRV_FLAGS_MAX (1 << 1)
#define SVGA3D_BUFFEREX_SRV_FLAGS_MASK (SVGA3D_BUFFEREX_SRV_FLAGS_MAX - 1)
typedef uint32 SVGA3dBufferExFlags;
typedef
#include "vmware_pack_begin.h"
......@@ -925,7 +1051,7 @@ struct {
struct {
uint32 firstElement;
uint32 numElements;
uint32 flags;
SVGA3dBufferExFlags flags;
uint32 pad0;
} bufferex;
};
......@@ -1072,6 +1198,32 @@ struct SVGA3dCmdDXDefineDepthStencilView {
SVGA3dCmdDXDefineDepthStencilView;
/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW */
/*
* Version 2 needed in order to start validating and using the flags
* field. Unfortunately the device wasn't validating or using the
* flags field and the driver wasn't initializing it in shipped code,
* so a new version of the command is needed to allow that code to
* continue to work.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineDepthStencilView_v2 {
SVGA3dDepthStencilViewId depthStencilViewId;
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
uint32 mipSlice;
uint32 firstArraySlice;
uint32 arraySize;
SVGA3DCreateDSViewFlags flags;
uint8 pad0;
uint16 pad1;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineDepthStencilView_v2;
/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyDepthStencilView {
......@@ -1081,6 +1233,138 @@ struct SVGA3dCmdDXDestroyDepthStencilView {
SVGA3dCmdDXDestroyDepthStencilView;
/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW */
#define SVGA3D_UABUFFER_RAW (1 << 0)
#define SVGA3D_UABUFFER_APPEND (1 << 1)
#define SVGA3D_UABUFFER_COUNTER (1 << 2)
typedef uint32 SVGA3dUABufferFlags;
typedef
#include "vmware_pack_begin.h"
struct {
union {
struct {
uint32 firstElement;
uint32 numElements;
SVGA3dUABufferFlags flags;
uint32 padding0;
uint32 padding1;
} buffer;
struct {
uint32 mipSlice;
uint32 firstArraySlice;
uint32 arraySize;
uint32 padding0;
uint32 padding1;
} tex; /* 1d, 2d */
struct {
uint32 mipSlice;
uint32 firstW;
uint32 wSize;
uint32 padding0;
uint32 padding1;
} tex3D;
};
}
#include "vmware_pack_end.h"
SVGA3dUAViewDesc;
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
SVGA3dUAViewDesc desc;
uint32 structureCount;
uint32 pad[7];
}
#include "vmware_pack_end.h"
SVGACOTableDXUAViewEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineUAView {
SVGA3dUAViewId uaViewId;
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
SVGA3dUAViewDesc desc;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineUAView;
/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyUAView {
SVGA3dUAViewId uaViewId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyUAView;
/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXClearUAViewUint {
SVGA3dUAViewId uaViewId;
SVGA3dRGBAUint32 value;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXClearUAViewUint;
/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXClearUAViewFloat {
SVGA3dUAViewId uaViewId;
SVGA3dRGBAFloat value;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXClearUAViewFloat;
/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXCopyStructureCount {
SVGA3dUAViewId srcUAViewId;
SVGA3dSurfaceId destSid;
uint32 destByteOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXCopyStructureCount;
/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetStructureCount {
SVGA3dUAViewId uaViewId;
uint32 structureCount;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetStructureCount;
/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetUAViews {
uint32 uavSpliceIndex;
/* Followed by a variable number of SVGA3dUAViewId's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetUAViews; /* SVGA_3D_CMD_DX_SET_UA_VIEWS */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetCSUAViews {
uint32 startIndex;
/* Followed by a variable number of SVGA3dUAViewId's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetCSUAViews; /* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dInputElementDesc {
......@@ -1099,7 +1383,7 @@ typedef
struct {
uint32 elid;
uint32 numDescs;
SVGA3dInputElementDesc desc[32];
SVGA3dInputElementDesc descs[32];
uint32 pad[62];
}
#include "vmware_pack_end.h"
......@@ -1261,7 +1545,8 @@ struct {
uint8 lineStippleEnable;
uint8 lineStippleFactor;
uint16 lineStipplePattern;
uint32 forcedSampleCount;
uint8 forcedSampleCount;
uint8 mustBeZero[3];
}
#include "vmware_pack_end.h"
SVGACOTableDXRasterizerStateEntry;
......@@ -1352,6 +1637,71 @@ struct SVGA3dCmdDXDestroySamplerState {
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
#define SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0
#define SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1
#define SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2
#define SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3
#define SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4
#define SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5
#define SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6
#define SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7
#define SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8
#define SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9
#define SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22
#define SVGADX_SIGNATURE_SEMANTIC_NAME_MAX 23
typedef uint32 SVGA3dDXSignatureSemanticName;
#define SVGADX_SIGNATURE_REGISTER_COMPONENT_UNKNOWN 0
typedef uint32 SVGA3dDXSignatureRegisterComponentType;
#define SVGADX_SIGNATURE_MIN_PRECISION_DEFAULT 0
typedef uint32 SVGA3dDXSignatureMinPrecision;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dDXSignatureEntry {
uint32 registerIndex;
SVGA3dDXSignatureSemanticName semanticName;
uint32 mask; /* Lower 4 bits represent X, Y, Z, W channels */
SVGA3dDXSignatureRegisterComponentType componentType;
SVGA3dDXSignatureMinPrecision minPrecision;
}
#include "vmware_pack_end.h"
SVGA3dDXShaderSignatureEntry;
#define SVGADX_SIGNATURE_HEADER_VERSION_0 0x08a92d12
/*
* The SVGA3dDXSignatureHeader structure is added after the shader
* body in the mob that is bound to the shader. It is followed by the
* specified number of SVGA3dDXSignatureEntry structures for each of
* the three types of signatures in the order (input, output, patch
* constants).
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dDXSignatureHeader {
uint32 headerVersion;
uint32 numInputSignatures;
uint32 numOutputSignatures;
uint32 numPatchConstantSignatures;
}
#include "vmware_pack_end.h"
SVGA3dDXShaderSignatureHeader;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineShader {
......@@ -1415,7 +1765,8 @@ SVGA3dCmdDXCondBindAllShader; /* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER */
/*
* The maximum number of streamout decl's in each streamout entry.
*/
#define SVGA3D_MAX_STREAMOUT_DECLS 64
#define SVGA3D_MAX_DX10_STREAMOUT_DECLS 64
#define SVGA3D_MAX_STREAMOUT_DECLS 512
typedef
#include "vmware_pack_begin.h"
......@@ -1434,10 +1785,16 @@ typedef
#include "vmware_pack_begin.h"
struct SVGAOTableStreamOutputEntry {
uint32 numOutputStreamEntries;
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS];
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
uint32 rasterizedStream;
uint32 pad[250];
uint32 numOutputStreamStrides;
uint32 mobid;
uint32 offsetInBytes;
uint8 usesMob;
uint8 pad0;
uint16 pad1;
uint32 pad2[246];
}
#include "vmware_pack_end.h"
SVGACOTableDXStreamOutputEntry;
......@@ -1447,13 +1804,47 @@ typedef
struct SVGA3dCmdDXDefineStreamOutput {
SVGA3dStreamOutputId soid;
uint32 numOutputStreamEntries;
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS];
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
uint32 rasterizedStream;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineStreamOutput; /* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT */
/*
* Version 2 needed in order to start validating and using the
* rasterizedStream field. Unfortunately the device wasn't validating
* or using this field and the driver wasn't initializing it in shipped
* code, so a new version of the command is needed to allow that code
* to continue to work. Also added new numOutputStreamStrides field.
*/
#define SVGA3D_DX_SO_NO_RASTERIZED_STREAM 0xFFFFFFFF
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineStreamOutputWithMob {
SVGA3dStreamOutputId soid;
uint32 numOutputStreamEntries;
uint32 numOutputStreamStrides;
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
uint32 rasterizedStream;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineStreamOutputWithMob;
/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBindStreamOutput {
SVGA3dStreamOutputId soid;
uint32 mobid;
uint32 offsetInBytes;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBindStreamOutput; /* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyStreamOutput {
......@@ -1470,6 +1861,15 @@ struct SVGA3dCmdDXSetStreamOutput {
#include "vmware_pack_end.h"
SVGA3dCmdDXSetStreamOutput; /* SVGA_3D_CMD_DX_SET_STREAMOUTPUT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetMinLOD {
SVGA3dSurfaceId sid;
float minLOD;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetMinLOD; /* SVGA_3D_CMD_DX_SET_MIN_LOD */
typedef
#include "vmware_pack_begin.h"
struct {
......@@ -1581,33 +1981,38 @@ struct SVGADXContextMobFormat {
uint32 rasterizerStateId;
uint32 depthStencilViewId;
uint32 renderTargetViewIds[SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS];
uint32 unorderedAccessViewIds[SVGA3D_MAX_UAVIEWS];
} renderState;
uint32 pad0[8];
struct {
uint32 targets[SVGA3D_DX_MAX_SOTARGETS];
uint32 soid;
} streamOut;
uint32 pad0[11];
uint32 pad1[10];
uint32 uavSpliceIndex;
uint8 numViewports;
uint8 numScissorRects;
uint16 pad1[1];
uint16 pad2[1];
uint32 pad2[3];
uint32 pad3[3];
SVGA3dViewport viewports[SVGA3D_DX_MAX_VIEWPORTS];
uint32 pad3[32];
uint32 pad4[32];
SVGASignedRect scissorRects[SVGA3D_DX_MAX_SCISSORRECTS];
uint32 pad4[64];
uint32 pad5[64];
struct {
uint32 queryID;
uint32 value;
} predication;
uint32 pad5[2];
SVGAMobId shaderIfaceMobid;
uint32 shaderIfaceOffset;
struct {
uint32 shaderId;
SVGA3dConstantBufferBinding constantBuffers[SVGA3D_DX_MAX_CONSTBUFFERS];
......@@ -1619,11 +2024,38 @@ struct SVGADXContextMobFormat {
SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
uint32 pad7[380];
uint32 pad7[64];
uint32 uaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
uint32 csuaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
uint32 pad8[188];
}
#include "vmware_pack_end.h"
SVGADXContextMobFormat;
/*
* There is conflicting documentation on max class instances (253 vs 256). The
* lower value is the one used throughout the device, but since mob format is
* more involved to increase if needed, conservatively use the higher one here.
*/
#define SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED 256
typedef
#include "vmware_pack_begin.h"
struct SVGADXShaderIfaceMobFormat {
struct {
uint32 numClassInstances;
uint32 iface[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
SVGA3dIfaceData data[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
} shaderIfaceState[SVGA3D_NUM_SHADERTYPE];
uint32 pad0[1018];
}
#include "vmware_pack_end.h"
SVGADXShaderIfaceMobFormat;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXTempSetContext {
......
drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
浏览文件 @ 0651dfab
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 2007-2015 VMware, Inc.
* Copyright 2007-2019 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
......@@ -40,11 +40,25 @@
#include "includeCheck.h"
#define SVGA3D_NUM_CLIPPLANES 6
#define SVGA3D_MAX_CONTEXT_IDS 256
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
/*
* While there are separate bind-points for RenderTargetViews and
* UnorderedAccessViews in a DXContext, there is in fact one shared
* semantic space that the guest-driver can use on any given draw call.
* So there are really only 8 slots that can be spilt up between them, with the
* spliceIndex controlling where the UAV's sit in the collapsed array.
*/
#define SVGA3D_MAX_RENDER_TARGETS 8
#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
#define SVGA3D_MAX_UAVIEWS 8
#define SVGA3D_MAX_CONTEXT_IDS 256
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
#define SVGA3D_DX11_1_MAX_UAVIEWS 64
/*
* Maximum canonical size of a surface in host-backed mode (pre-GBObjects).
*/
#define SVGA3D_HB_MAX_SURFACE_SIZE MBYTES_2_BYTES(128)
/*
* Maximum ID a shader can be assigned on a given context.
......@@ -59,6 +73,8 @@
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
/*
* Maximum size in dwords of shader text the SVGA device will allow.
* Currently 8 MB.
......@@ -67,6 +83,11 @@
#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
sizeof(uint32))
/*
* The maximum value of threadGroupCount in each dimension
*/
#define SVGA3D_MAX_SHADER_THREAD_GROUPS 65535
#define SVGA3D_MAX_CLIP_PLANES 6
/*
......@@ -85,7 +106,9 @@
/*
* Maximum number of array indexes in a GB surface (with DX enabled).
*/
#define SVGA3D_MAX_SURFACE_ARRAYSIZE 512
#define SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE 512
#define SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE 2048
#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
/*
* The maximum number of vertex arrays we're guaranteed to support in
......@@ -99,4 +122,9 @@
*/
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
/*
* The maximum number of samples that can be contained in a surface.
*/
#define SVGA3D_MAX_SAMPLES 8
#endif /* _SVGA3D_LIMITS_H_ */
drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
浏览文件 @ 0651dfab
......@@ -131,6 +131,8 @@ enum svga3d_block_desc {
SVGA3DBLOCKDESC_BC3 = 1 << 26,
SVGA3DBLOCKDESC_BC4 = 1 << 27,
SVGA3DBLOCKDESC_BC5 = 1 << 28,
SVGA3DBLOCKDESC_BC6H = 1 << 29,
SVGA3DBLOCKDESC_BC7 = 1 << 30,
SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA |
SVGA3DBLOCKDESC_UINT |
......@@ -290,6 +292,18 @@ enum svga3d_block_desc {
SVGA3DBLOCKDESC_COMP_UNORM,
SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 |
SVGA3DBLOCKDESC_COMP_SNORM,
SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H |
SVGA3DBLOCKDESC_COMP_TYPELESS,
SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H |
SVGA3DBLOCKDESC_COMPRESSED,
SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H |
SVGA3DBLOCKDESC_COMPRESSED,
SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 |
SVGA3DBLOCKDESC_COMP_TYPELESS,
SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 |
SVGA3DBLOCKDESC_COMP_UNORM,
SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM |
SVGA3DBLOCKDESC_SRGB,
SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO |
SVGA3DBLOCKDESC_PLANAR_YUV |
......@@ -494,7 +508,7 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
{{8}, {8}, {8}, {0}},
{{16}, {8}, {0}, {0}}},
{SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_UVL,
{SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE,
{1, 1, 1}, 3, 3,
{{8}, {8}, {8}, {0}},
{{16}, {8}, {0}, {0}}},
......@@ -604,7 +618,7 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
{{0}, {0}, {48}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
{SVGA3D_FORMAT_DEAD2, SVGA3DBLOCKDESC_NONE,
{1, 1, 1}, 4, 4,
{{8}, {8}, {8}, {8}},
{{0}, {8}, {16}, {24}}},
......@@ -1103,6 +1117,46 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
{4, 4, 1}, 16, 16,
{{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
{1, 1, 1}, 2, 2,
{{4}, {4}, {4}, {4}},
{{0}, {4}, {8}, {12}}},
{SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS,
{4, 4, 1}, 16, 16,
{{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16,
{4, 4, 1}, 16, 16,
{{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16,
{4, 4, 1}, 16, 16,
{{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS,
{4, 4, 1}, 16, 16,
{{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM,
{4, 4, 1}, 16, 16,
{{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB,
{4, 4, 1}, 16, 16,
{{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
{1, 1, 1}, 4, 4,
{{8}, {8}, {8}, {8}},
{{0}, {8}, {16}, {24}}},
};
static inline u32 clamped_umul32(u32 a, u32 b)
......
drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
浏览文件 @ 0651dfab
......@@ -70,8 +70,7 @@ typedef uint32 SVGAMobId;
/*
* Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
* cursor bypass mode. This is still supported, but no new guest
* drivers should use it.
* cursor bypass mode.
*/
#define SVGA_CURSOR_ON_HIDE 0x0
#define SVGA_CURSOR_ON_SHOW 0x1
......@@ -136,6 +135,17 @@ typedef uint32 SVGAMobId;
#define SVGA_IRQFLAG_COMMAND_BUFFER 0x8 /* Command buffer completed */
#define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */
/*
* The byte-size is the size of the actual cursor data,
* possibly after expanding it to the current bit depth.
*
* 40K is sufficient memory for two 32-bit planes for a 64 x 64 cursor.
*
* The dimension limit is a bound on the maximum width or height.
*/
#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024)
#define SVGA_MAX_CURSOR_CMD_DIMENSION 1024
/*
* Registers
*/
......@@ -169,7 +179,7 @@ enum {
SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
SVGA_REG_GUEST_ID = 23, /* (Deprecated) */
SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */
SVGA_REG_DEAD = 24, /* Drivers should never write this. */
SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */
......@@ -208,7 +218,13 @@ enum {
SVGA_REG_MAX_PRIMARY_MEM = 50,
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
/*
* Legacy version of SVGA_REG_GBOBJECT_MEM_SIZE_KB for drivers that
* don't know how to convert to a 64-bit byte value without overflowing.
* (See SVGA_REG_GBOBJECT_MEM_SIZE_KB).
*/
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51,
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
SVGA_REG_CMD_PREPEND_LOW = 53,
SVGA_REG_CMD_PREPEND_HIGH = 54,
......@@ -218,7 +234,59 @@ enum {
SVGA_REG_BLANK_SCREEN_TARGETS = 58,
SVGA_REG_CAP2 = 59,
SVGA_REG_DEVEL_CAP = 60,
SVGA_REG_TOP = 61, /* Must be 1 more than the last register */
/*
* Allow the guest to hint to the device which driver is running.
*
* This should not generally change device behavior, but might be
* convenient to work-around specific bugs in guest drivers.
*
* Drivers should first write their id value into SVGA_REG_GUEST_DRIVER_ID,
* and then fill out all of the version registers that they have defined.
*
* After the driver has written all of the registers, they should
* then write the value SVGA_REG_GUEST_DRIVER_ID_SUBMIT to the
* SVGA_REG_GUEST_DRIVER_ID register, to signal that they have finished.
*
* The SVGA_REG_GUEST_DRIVER_ID values are defined below by the
* SVGARegGuestDriverId enum.
*
* The SVGA_REG_GUEST_DRIVER_VERSION fields are driver-specific,
* but ideally should encode a monotonically increasing number that allows
* the device to perform inequality checks against ranges of driver versions.
*/
SVGA_REG_GUEST_DRIVER_ID = 61,
SVGA_REG_GUEST_DRIVER_VERSION1 = 62,
SVGA_REG_GUEST_DRIVER_VERSION2 = 63,
SVGA_REG_GUEST_DRIVER_VERSION3 = 64,
SVGA_REG_CURSOR_MOBID = 65,
SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66,
SVGA_REG_CURSOR_MAX_DIMENSION = 67,
SVGA_REG_FIFO_CAPS = 68,
SVGA_REG_FENCE = 69,
SVGA_REG_RESERVED1 = 70,
SVGA_REG_RESERVED2 = 71,
SVGA_REG_RESERVED3 = 72,
SVGA_REG_RESERVED4 = 73,
SVGA_REG_RESERVED5 = 74,
SVGA_REG_SCREENDMA = 75,
/*
* The maximum amount of guest-backed objects that the device can have
* resident at a time. Guest-drivers should keep their working set size
* below this limit for best performance.
*
* Note that this value is in kilobytes, and not bytes, because the actual
* number of bytes might be larger than can fit in a 32-bit register.
*
* PLEASE USE A 64-BIT VALUE WHEN CONVERTING THIS INTO BYTES.
* (See SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB).
*/
SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76,
SVGA_REG_TOP = 77, /* Must be 1 more than the last register */
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
/* Next 768 (== 256*3) registers exist for colormap */
......@@ -229,6 +297,20 @@ enum {
the use of the current SVGA driver. */
};
/*
* Values for SVGA_REG_GUEST_DRIVER_ID.
*/
typedef enum SVGARegGuestDriverId {
SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0,
SVGA_REG_GUEST_DRIVER_ID_WDDM = 1,
SVGA_REG_GUEST_DRIVER_ID_LINUX = 2,
SVGA_REG_GUEST_DRIVER_ID_MAX,
SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32,
} SVGARegGuestDriverId;
/*
* Guest memory regions (GMRs):
*
......@@ -416,7 +498,6 @@ typedef enum {
SVGA_CB_CONTEXT_0 = 0x0,
SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
SVGA_CB_CONTEXT_MAX = 0x2,
SVGA_CB_CONTEXT_HP_MAX = 0x2,
} SVGACBContext;
......@@ -733,9 +814,6 @@ SVGASignedPoint;
* and must not be reused. Those capabilities will never be reported
* by new versions of the SVGA device.
*
* XXX: Add longer descriptions for each capability, including a list
* of the new features that each capability provides.
*
* SVGA_CAP_IRQMASK --
* Provides device interrupts. Adds device register SVGA_REG_IRQMASK
* to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
......@@ -842,17 +920,51 @@ SVGASignedPoint;
* Allow the IntraSurfaceCopy command.
*
* SVGA_CAP2_DX2 --
* Allow the DefineGBSurface_v3, WholeSurfaceCopy.
* Allow the DefineGBSurface_v3, WholeSurfaceCopy, WriteZeroSurface, and
* HintZeroSurface commands, and the SVGA_REG_GUEST_DRIVER_ID register.
*
* SVGA_CAP2_GB_MEMSIZE_2 --
* Allow the SVGA_REG_GBOBJECT_MEM_SIZE_KB register.
*
* SVGA_CAP2_SCREENDMA_REG --
* Allow the SVGA_REG_SCREENDMA register.
*
* SVGA_CAP2_OTABLE_PTDEPTH_2 --
* Allow 2 level page tables for OTable commands.
*
* SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT --
* Allow a stretch blt from a non-multisampled surface to a multisampled
* surface.
*
* SVGA_CAP2_CURSOR_MOB --
* Allow the SVGA_REG_CURSOR_MOBID register.
*
* SVGA_CAP2_MSHINT --
* Allow the SVGA_REG_MSHINT register.
*
* SVGA_CAP2_DX3 --
* Allows the DefineGBSurface_v4 command.
* Allows the DXDefineDepthStencilView_v2, DXDefineStreamOutputWithMob,
* and DXBindStreamOutput commands if 3D is also available.
* Allows the DXPredStagingCopy and DXStagingCopy commands if SM41
* is also available.
*
* SVGA_CAP2_RESERVED --
* Reserve the last bit for extending the SVGA capabilities to some
* future mechanisms.
*/
#define SVGA_CAP2_NONE 0x00000000
#define SVGA_CAP2_GROW_OTABLE 0x00000001
#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
#define SVGA_CAP2_DX2 0x00000004
#define SVGA_CAP2_RESERVED 0x80000000
#define SVGA_CAP2_NONE 0x00000000
#define SVGA_CAP2_GROW_OTABLE 0x00000001
#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
#define SVGA_CAP2_DX2 0x00000004
#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008
#define SVGA_CAP2_SCREENDMA_REG 0x00000010
#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020
#define SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT 0x00000040
#define SVGA_CAP2_CURSOR_MOB 0x00000080
#define SVGA_CAP2_MSHINT 0x00000100
#define SVGA_CAP2_DX3 0x00000400
#define SVGA_CAP2_RESERVED 0x80000000
/*
......@@ -875,7 +987,9 @@ typedef enum {
SVGABackdoorCapFifoCaps = 1,
SVGABackdoorCap3dHWVersion = 2,
SVGABackdoorCapDeviceCaps2 = 3,
SVGABackdoorCapMax = 4,
SVGABackdoorCapDevelCaps = 4,
SVGABackdoorDevelRenderer = 5,
SVGABackdoorCapMax = 6,
} SVGABackdoorCapType;
......@@ -1055,103 +1169,80 @@ enum {
/*
* FIFO Synchronization Registers
*
* This explains the relationship between the various FIFO
* sync-related registers in IOSpace and in FIFO space.
*
* SVGA_REG_SYNC --
*
* The SYNC register can be used in two different ways by the guest:
*
* 1. If the guest wishes to fully sync (drain) the FIFO,
* it will write once to SYNC then poll on the BUSY
* register. The FIFO is sync'ed once BUSY is zero.
*
* 2. If the guest wants to asynchronously wake up the host,
* it will write once to SYNC without polling on BUSY.
* Ideally it will do this after some new commands have
* been placed in the FIFO, and after reading a zero
* from SVGA_FIFO_BUSY.
*
* (1) is the original behaviour that SYNC was designed to
* support. Originally, a write to SYNC would implicitly
* trigger a read from BUSY. This causes us to synchronously
* process the FIFO.
*
* This behaviour has since been changed so that writing SYNC
* will *not* implicitly cause a read from BUSY. Instead, it
* makes a channel call which asynchronously wakes up the MKS
* thread.
*
* New guests can use this new behaviour to implement (2)
* efficiently. This lets guests get the host's attention
* without waiting for the MKS to poll, which gives us much
* better CPU utilization on SMP hosts and on UP hosts while
* we're blocked on the host GPU.
*
* Old guests shouldn't notice the behaviour change. SYNC was
* never guaranteed to process the entire FIFO, since it was
* bounded to a particular number of CPU cycles. Old guests will
* still loop on the BUSY register until the FIFO is empty.
*
* Writing to SYNC currently has the following side-effects:
*
* - Sets SVGA_REG_BUSY to TRUE (in the monitor)
* - Asynchronously wakes up the MKS thread for FIFO processing
* - The value written to SYNC is recorded as a "reason", for
* stats purposes.
*
* If SVGA_FIFO_BUSY is available, drivers are advised to only
* write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
* SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
* eventually set SVGA_FIFO_BUSY on its own, but this approach
* lets the driver avoid sending multiple asynchronous wakeup
* messages to the MKS thread.
* The SYNC register can be used by the guest driver to signal to the
* device that the guest driver is waiting for previously submitted
* commands to complete.
*
* When the guest driver writes to the SYNC register, the device sets
* the BUSY register to TRUE, and starts processing the submitted commands
* (if it was not already doing so). When all previously submitted
* commands are finished and the device is idle again, it sets the BUSY
* register back to FALSE. (If the guest driver submits new commands
* after writing the SYNC register, the new commands are not guaranteed
* to have been procesesd.)
*
* When guest drivers are submitting commands using the FIFO, the device
* periodically polls to check for new FIFO commands when idle, which may
* introduce a delay in command processing. If the guest-driver wants
* the commands to be processed quickly (which it typically does), it
* should write SYNC after each batch of commands is committed to the
* FIFO to immediately wake up the device. For even better performance,
* the guest can use the SVGA_FIFO_BUSY register to avoid these extra
* SYNC writes if the device is already active, using the technique known
* as "Ringing the Doorbell" (described below). (Note that command
* buffer submission implicitly wakes up the device, and so doesn't
* suffer from this problem.)
*
* The SYNC register can also be used in combination with BUSY to
* synchronously ensure that all SVGA commands are processed (with both
* the FIFO and command-buffers). To do this, the guest driver should
* write to SYNC, and then loop reading BUSY until BUSY returns FALSE.
* This technique is known as a "Legacy Sync".
*
* SVGA_REG_BUSY --
*
* This register is set to TRUE when SVGA_REG_SYNC is written,
* and it reads as FALSE when the FIFO has been completely
* drained.
*
* Every read from this register causes us to synchronously
* process FIFO commands. There is no guarantee as to how many
* commands each read will process.
* and is set back to FALSE when the device has finished processing
* all commands and is idle again.
*
* CPU time spent processing FIFO commands will be billed to
* the guest.
* Every read from the BUSY reigster will block for an undefined
* amount of time (normally until the device finishes some interesting
* work unit), or the device is idle.
*
* New drivers should avoid using this register unless they
* need to guarantee that the FIFO is completely drained. It
* is overkill for performing a sync-to-fence. Older drivers
* will use this register for any type of synchronization.
* Guest drivers can also do a partial Legacy Sync to check for some
* particular condition, for instance by stopping early when a fence
* passes before BUSY has been set back to FALSE. This is particularly
* useful if the guest-driver knows that it is blocked waiting on the
* device, because it will yield CPU time back to the host.
*
* SVGA_FIFO_BUSY --
*
* This register is a fast way for the guest driver to check
* whether the FIFO is already being processed. It reads and
* writes at normal RAM speeds, with no monitor intervention.
*
* If this register reads as TRUE, the host is guaranteeing that
* any new commands written into the FIFO will be noticed before
* the MKS goes back to sleep.
* The SVGA_FIFO_BUSY register is a fast way for the guest driver to check
* whether the device is actively processing FIFO commands before writing
* the more expensive SYNC register.
*
* If this register reads as FALSE, no such guarantee can be
* made.
* If this register reads as TRUE, the device is actively processing
* FIFO commands.
*
* The guest should use this register to quickly determine
* whether or not it needs to wake up the host. If the guest
* just wrote a command or group of commands that it would like
* the host to begin processing, it should:
* If this register reads as FALSE, the device may not be actively
* processing commands, and the guest driver should try
* "Ringing the Doorbell".
*
* 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
* action is necessary.
* To Ring the Doorbell, the guest should:
*
* 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
* code that we've already sent a SYNC to the host and we
* don't need to send a duplicate.
* 1. Have already written their batch of commands into the FIFO.
* 2. Check if the SVGA_FIFO_BUSY register is available by reading
* SVGA_FIFO_MIN.
* 3. Read SVGA_FIFO_BUSY. If it reads as TRUE, the device is actively
* processing FIFO commands, and no further action is necessary.
* 4. If SVGA_FIFO_BUSY was FALSE, write TRUE to SVGA_REG_SYNC.
*
* 3. Write a reason to SVGA_REG_SYNC. This will send an
* asynchronous wakeup to the MKS thread.
* For maximum performance, this procedure should be followed after
* every meaningful batch of commands has been written into the FIFO.
* (Normally when the underlying application signals it's finished a
* meaningful work unit by calling Flush.)
*/
......@@ -1164,9 +1255,6 @@ enum {
* Video -- SVGA Video overlay units are supported
* Escape -- Escape command is supported
*
* XXX: Add longer descriptions for each capability, including a list
* of the new features that each capability provides.
*
* SVGA_FIFO_CAP_SCREEN_OBJECT --
*
* Provides dynamic multi-screen rendering, for improved Unity and
......@@ -1278,6 +1366,15 @@ enum {
#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
/*
* ScreenDMA Register Values
*/
#define SVGA_SCREENDMA_REG_UNDEFINED 0
#define SVGA_SCREENDMA_REG_NOT_PRESENT 1
#define SVGA_SCREENDMA_REG_PRESENT 2
#define SVGA_SCREENDMA_REG_MAX 3
/*
* Video overlay support
*/
......@@ -1664,6 +1761,80 @@ struct {
SVGAFifoCmdDefineAlphaCursor;
/*
* Provide a new large cursor image, as an AND/XOR mask.
*
* Should only be used for CursorMob functionality
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 hotspotX;
uint32 hotspotY;
uint32 width;
uint32 height;
uint32 andMaskDepth;
uint32 xorMaskDepth;
/*
* Followed by scanline data for AND mask, then XOR mask.
* Each scanline is padded to a 32-bit boundary.
*/
}
#include "vmware_pack_end.h"
SVGAGBColorCursorHeader;
/*
* Provide a new large cursor image, in 32-bit BGRA format.
*
* Should only be used for CursorMob functionality
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 hotspotX;
uint32 hotspotY;
uint32 width;
uint32 height;
/* Followed by scanline data */
}
#include "vmware_pack_end.h"
SVGAGBAlphaCursorHeader;
/*
* Define the SVGA guest backed cursor types
*/
typedef enum {
SVGA_COLOR_CURSOR = 0,
SVGA_ALPHA_CURSOR = 1,
} SVGAGBCursorType;
/*
* Provide a new large cursor image.
*
* Should only be used for CursorMob functionality
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGAGBCursorType type;
union {
SVGAGBColorCursorHeader colorHeader;
SVGAGBAlphaCursorHeader alphaHeader;
} header;
uint32 sizeInBytes;
/*
* Followed by the cursor data
*/
}
#include "vmware_pack_end.h"
SVGAGBCursorHeader;
/*
* SVGA_CMD_UPDATE_VERBOSE --
*
......@@ -2061,9 +2232,12 @@ SVGAFifoCmdRemapGMR2;
#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_2GB (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_3GB (3 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_4GB (4 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_8GB (8 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
......@@ -2086,4 +2260,6 @@ SVGAFifoCmdRemapGMR2;
#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
#define SVGA_PCI_REGS_PAGES (1)
#endif
drivers/gpu/drm/vmwgfx/device_include/svga_types.h
浏览文件 @ 0651dfab
......@@ -37,6 +37,7 @@ typedef s8 int8;
typedef uint64 PA;
typedef uint32 PPN;
typedef uint32 PPN32;
typedef uint64 PPN64;
typedef bool Bool;
......
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