arm64: Add MIDR encoding for PHYTIUM CPUs

uniontech inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I41AUQ
CVE: NA

-------------------------------------

Adding the MIDR encodings for PHYTIUM 2000+ and 2500 CPUs.
Signed-off-by: NGuo Hui <guohui@uniontech.com>
Signed-off-by: NHanjun Guo <guohanjun@huawei.com>
Cc: Guo Hui <guohui@uniontech.com>
Cc: Cheng Jian <cj.chengjian@huawei.com>
Cc: Zhen Lei <thunder.leizhen@huawei.com>
Cc: Xiuqi Xie <xiexiuqi@huawei.com>
Reviewed-by: NXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: NCheng Jian <cj.chengjian@huawei.com>

arch/arm64/include/asm/cputype.h

@@ -101,6 +101,9 @@
 #define HISI_CPU_PART_TSV110		0xD01
 #define HISI_CPU_PART_TSV200		0xD02
 
+#define PHYTIUM_CPU_PART_FTC662		0x662
+#define PHYTIUM_CPU_PART_FTC663		0x663
+
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -121,6 +124,8 @@
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
 #define MIDR_HISI_TSV200 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV200)
+#define MIDR_PHYTIUM_FT2000PLUS MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC662)
+#define MIDR_PHYTIUM_FT2500 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC663)
 
 #ifndef __ASSEMBLY__