arm64/sme: Standardise bitfield names for SVCR

mainline inclusion
from mainline-v5.19-rc1
commit e65fc01b
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5ITJT
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e65fc01bf271cefa6269b7ab1badcf7cddae5d40

-------------------------------------------------

The bitfield definitions for SVCR have a SYS_ added to the names of the
constant which will be a problem for automatic generation. Remove the
prefixes, no functional change.
Signed-off-by: NMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220510161208.631259-5-broonie@kernel.orgSigned-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWang ShaoBo <bobo.shaobowang@huawei.com>

arch/arm64/include/asm/fpsimd.h

@@ -68,12 +68,12 @@ extern void fpsimd_save_and_flush_cpu_state(void);
 
 static inline bool thread_sm_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK);
 }
 
 static inline bool thread_za_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_ZA_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_EL0_ZA_MASK);
 }
 
 /* Maximum VL that SVE/SME VL-agnostic software can transparently support */

arch/arm64/include/asm/processor.h

@@ -192,7 +192,7 @@ static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
 
 static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
 {
-	if (system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK))
+	if (system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK))
 		return thread_get_sme_vl(thread);
 	else
 		return thread_get_sve_vl(thread);

arch/arm64/include/asm/sysreg.h

@@ -413,8 +413,8 @@
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
 
 #define SYS_SVCR_EL0			sys_reg(3, 3, 4, 2, 2)
-#define SYS_SVCR_EL0_ZA_MASK		2
-#define SYS_SVCR_EL0_SM_MASK		1
+#define SVCR_EL0_ZA_MASK		2
+#define SVCR_EL0_SM_MASK		1
 
 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)

arch/arm64/kernel/fpsimd.c

@@ -1878,7 +1878,7 @@ void __efi_fpsimd_begin(void)
 				svcr = read_sysreg_s(SYS_SVCR_EL0);
 
 				if (!system_supports_fa64())
-					ffr = svcr & SYS_SVCR_EL0_SM_MASK;
+					ffr = svcr & SVCR_EL0_SM_MASK;
 
 				__this_cpu_write(efi_sm_state, ffr);
 			}
@@ -1889,7 +1889,7 @@ void __efi_fpsimd_begin(void)
 
 			if (system_supports_sme())
 				sysreg_clear_set_s(SYS_SVCR_EL0,
-						   SYS_SVCR_EL0_SM_MASK, 0);
+						   SVCR_EL0_SM_MASK, 0);
 
 		} else {
 			fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
@@ -1924,7 +1924,7 @@ void __efi_fpsimd_end(void)
 				if (__this_cpu_read(efi_sm_state)) {
 					sysreg_clear_set_s(SYS_SVCR_EL0,
 							   0,
-							   SYS_SVCR_EL0_SM_MASK);
+							   SVCR_EL0_SM_MASK);
 					if (!system_supports_fa64())
 						ffr = efi_sm_state;
 				}