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    [PATCH] PCI: PCIE power management quirk · ffadcc2f
    Kristen Carlson Accardi 提交于
    When changing power states from D0->DX and then from DX->D0, some
    Intel PCIE chipsets will cause a device reset to occur.  This will
    cause problems for any D State other than D3, since any state
    information that the driver will expect to be present coming from
    a D1 or D2 state will have been cleared.  This patch addes a
    flag to the pci_dev structure to indicate that devices should
    not use states D1 or D2, and will set that flag for the affected
    chipsets.  This patch also modifies pci_set_power_state() so that
    when a device driver tries to set the power state on
    a device that is downstream from an affected chipset, or on one
    of the affected devices it only allows state changes to or
    from D0 & D3.  In addition, this patch allows the delay time
    between D3->D0 to be changed via a quirk.  These chipsets also
    need additional time to change states beyond the normal 10ms.
    Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
    Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
    ffadcc2f
quirks.c 55.6 KB