EDMA based chips (AR9380+) have 8 Tx FIFO slots, which are used to fix the
tx queue start/stop race conditions which have to be worked around for
earlier chips by keeping the last descriptor in the queue. The current code
stores all frames that do not fit onto the 8 FIFO slots in a separate
list. Whenever a FIFO slot is freed up, the next frame (or A-MPDU) from the
pending queue gets moved to that slot.

This process is not only inefficient, but also unnecessary. The code can
be improved visibly by keeping the pending queue fully linked, and moving
the contents of the entire queue to a FIFO slot as it becomes available.

This patch makes the necessary changes for that and also merges some code
that was duplicated for EDMA vs non-EDMA. It changes txq->axq_link to point
to the last descriptor instead of the link pointer, so that
ath9k_hw_set_desc_link can be used, which works on all chips.

With this patch, a small performance increase for non-aggregated traffic
was observed on AR9380 based embedded hardware.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>