The members "dma_addr_t command_orb_dma" and "dma_addr_t sge_dma" of
sbp2.h::sbp2_command_info do not have to be aligned themselves --- only
the memory which they point to has to be.

The member "struct sbp2_command_orb command_orb" has to be aligned on
4 bytes boundary which is guaranteed because it contains u32 members.

The member "struct sbp2_unrestricted_page_table scatter_gather_element",
i.e. the SBP-2 s/g table, has to be aligned on 8 bytes boundary
according to the SBP-2 spec.  This is not a requirement for FireWire
controllers but could be expected by SBP-2 targets.

I see no need to align the members command_orb and
scatter_gather_element on CPU cacheline boundaries.  It could have
performance benefits, but on the other hand sbp2 has a somewhat wasteful
allocation scheme which should be optimized first before further tweaks
like cacheline alignments.  (E.g. don't always allocate SG_ALL s/g table
elements.)

Note, before as well as after the patch, the code relies on the
assumption that memory alignment in the virtual address space is
preserved in the physical address space after DMA mapping.
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>