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    drm/i915/bdw: Reorganize PPGTT init · f3a964b9
    Ben Widawsky 提交于
    Create 3 clear stages in PPGTT init. This will help with upcoming
    changes be more readable. The 3 stages are, allocation, dma mapping, and
    writing the P[DT]Es
    
    One nice benefit to the patches is that it makes 2 very clear error
    points, allocation, and mapping, and avoids having to do any handling
    after writing PTEs (something which was likely buggy before). This
    simplified error handling I suspect will be helpful when we move to
    deferred/dynamic page table allocation and mapping.
    
    The patches also attempts to break up some of the steps into more
    logical reviewable chunks, particularly when we free.
    
    v2: Don't call cleanup on the error path since that takes down the
    drm_mm and list entry, which aren't setup at this point.
    
    v3: Fixes addressing Imre's comments from:
    <1392821989.19792.13.camel@intelbox>
    
    Don't do dynamic allocation for the page table DMA addresses. I can't
    remember why I did it in the first place. This addresses one of Imre's
    other issues.
    
    Fix error path leak of page tables.
    
    v4: Fix the fix of the error path leak. Original fix still leaked page
    tables. (Imre)
    Reviewed-by: NImre Deak <imre.deak@intel.com>
    Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    f3a964b9
i915_gem_gtt.c 52.1 KB