• N
    powerpc/64s: flush L1D after user accesses · f2671aa6
    Nicholas Piggin 提交于
    stable inclusion
    from linux-4.19.159
    commit 31ebc2fe02df202566d0e36c1106b4902d6e2f8c
    CVE: CVE-2020-4788
    
    --------------------------------
    
    commit 9a32a7e7 upstream.
    
    IBM Power9 processors can speculatively operate on data in the L1 cache before
    it has been completely validated, via a way-prediction mechanism. It is not possible
    for an attacker to determine the contents of impermissible memory using this method,
    since these systems implement a combination of hardware and software security measures
    to prevent scenarios where protected data could be leaked.
    
    However these measures don't address the scenario where an attacker induces
    the operating system to speculatively execute instructions using data that the
    attacker controls. This can be used for example to speculatively bypass "kernel
    user access prevention" techniques, as discovered by Anthony Steinhauser of
    Google's Safeside Project. This is not an attack by itself, but there is a possibility
    it could be used in conjunction with side-channels or other weaknesses in the
    privileged code to construct an attack.
    
    This issue can be mitigated by flushing the L1 cache between privilege boundaries
    of concern. This patch flushes the L1 cache after user accesses.
    
    This is part of the fix for CVE-2020-4788.
    Signed-off-by: NNicholas Piggin <npiggin@gmail.com>
    Signed-off-by: NDaniel Axtens <dja@axtens.net>
    Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
    Reviewed-by: NJason Yan <yanaijie@huawei.com>
    Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
    f2671aa6
feature-fixups.c 23.2 KB