• K
    drm/i915: Correct eDP panel power sequencing delay computations · f01eca2e
    Keith Packard 提交于
    Store the panel power sequencing delays in the dp private structure,
    rather than the global device structure. Who knows, maybe we'll get
    more than one eDP device in the future.
    
    From the eDP spec, we need the following numbers:
    
     T1 + T3	Power on to Aux Channel operation (panel_power_up_delay)
    
    		This marks how long it takes the panel to boot up and
    		get ready to receive aux channel communications.
    
     T8		Video signal to backlight on (backlight_on_delay)
    
    		Once a valid video signal is being sent to the device,
    		it can take a while before the panel is actuall
    		showing useful data. This delay allows the panel
    		to get something reasonable up before the backlight
    		is turned on.
    
     T9		Backlight off to video off (backlight_off_delay)
    
    		Turning the backlight off can take a moment, so
    		this delay makes sure there is still valid video
    		data on the screen.
    
     T10		Video off to power off (panel_power_down_delay)
    
    		Presumably this delay allows the panel to perform
    		an orderly shutdown of the display.
    
     T11 + T12	Power off to power on (panel_power_cycle_delay)
    
    		So, once you turn the panel off, you have to wait a
    		while before you can turn it back on. This delay is
    		usually the longest in the entire sequence.
    
    Neither the VBIOS source code nor the hardware documentation has a
    clear mapping between the delay values they provide and those required
    by the eDP spec. The VBIOS code actually uses two different labels for
    the delay values in the five words of the relevant VBT table.
    
    **** MORE LATER ***
    
    Look at both the current hardware register settings and the VBT
    specified panel power sequencing timings. Use the maximum of the two
    delays, to make sure things work reliably. If there is no VBT data,
    then those values will be initialized to zero, so we'll just use the
    values as programmed in the hardware. Note that the BIOS just fetches
    delays from the VBT table to place in the hardware registers, so we
    should get the same values from both places, except for rounding.
    
    VBT doesn't provide any values for T1 or T2, so we'll always just use
    the hardware value for that.
    
    The panel power up delay is thus T1 + T2 + T3, which should be
    sufficient in all cases.
    
    The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
    for T11, which isn't available anywhere.
    
    For the backlight delays, the eDP spec says T6 + T8 is the delay from the
    end of link training to backlight on and T9 is the delay from
    backlight off until video off. The hardware provides a 'backlight on'
    delay, which I'm taking to be T6 + T8 while the VBT provides something
    called 'T7', which I'm assuming is s
    
    On the macbook air I'm testing with, this yields a power-up delay of
    over 200ms and a power-down delay of over 600ms. It all works now, but
    we're frobbing these power controls several times during mode setting,
    making the whole process take an awfully long time.
    Signed-off-by: NKeith Packard <keithp@keithp.com>
    f01eca2e
intel_dp.c 58.3 KB