The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
    C66x_0 DSP: j7-c66_0-fw
    C66x_1 DSP: j7-c66_1-fw
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-3-s-anna@ti.com