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    Revert "PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge" · e4000dd2
    Marek Behún 提交于
    stable inclusion
    from stable-v5.10.85
    commit 391ca20ea16e0921840b8927f38b052d5657862a
    bugzilla: 186032 https://gitee.com/openeuler/kernel/issues/I4QVI4
    
    Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=391ca20ea16e0921840b8927f38b052d5657862a
    
    --------------------------------
    
    commit 39bd54d4 upstream.
    
    This reverts commit 239edf68.
    
    239edf68 ("PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated
    bridge") added support for the Type 1 Expansion ROM BAR at config offset
    0x38, based on the register being listed in the Marvell Armada A3720 spec.
    But the spec doesn't document it at all for RC mode, and there is no ROM in
    the SOC, so remove this emulation for now.
    
    The PCI bridge which represents aardvark's PCIe Root Port has an Expansion
    ROM Base Address register at offset 0x30, but its meaning is different than
    PCI's Expansion ROM BAR register, although the layout is the same.  (This
    is why we thought it does the same thing.)
    
    First: there is no ROM (or part of BootROM) in the A3720 SOC dedicated for
    PCIe Root Port (or controller in RC mode) containing executable code that
    would initialize the Root Port, suitable for execution in bootloader (this
    is how Expansion ROM BAR is used on x86).
    
    Second: in A3720 spec the register (address 0xD0070030) is not documented
    at all for Root Complex mode, but similar to other BAR registers, it has an
    "entangled partner" in register 0xD0075920, which does address translation
    for the BAR in 0xD0070030:
    
      - the BAR register sets the address from the view of PCIe bus
    
      - the translation register sets the address from the view of the CPU
    
    The other BAR registers also have this entangled partner, and they can be
    used to:
    
      - in RC mode: address-checking on the receive side of the RC (they can
        define address ranges for memory accesses from remote Endpoints to the
        RC)
    
      - in Endpoint mode: allow the remote CPU to access memory on A3720
    
    The Expansion ROM BAR has only the Endpoint part documented, but from the
    similarities we think that it can also be used in RC mode in that way.
    
    So either Expansion ROM BAR has different meaning (if the hypothesis above
    is true), or we don't know it's meaning (since it is not documented for RC
    mode).
    
    Remove the register from the emulated bridge accessing functions.
    
    [bhelgaas: summarize reason for removal (first paragraph)]
    Fixes: 239edf68 ("PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge")
    Link: https://lore.kernel.org/r/20211125160148.26029-3-kabel@kernel.orgSigned-off-by: NMarek Behún <kabel@kernel.org>
    Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: NPali Rohár <pali@kernel.org>
    Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    Signed-off-by: NChen Jun <chenjun102@huawei.com>
    Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
    e4000dd2
pci-aardvark.c 49.8 KB