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    drm/amdgpu: Set GTT_USWC flag to enable freesync v2 · e36ccf9a
    Shashank Sharma 提交于
    This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input
    parameter flag, during object creation of an imported DMA
    buffer.
    
    In absence of this flag:
    1. Function amdgpu_display_supported_domains() doesn't add
       AMDGPU_GEM_DOMAIN_GTT as supported domain.
    2. Due to which, Function amdgpu_display_user_framebuffer_create()
       refuses to create framebuffer for imported DMA buffers.
    3. Due to which, AddFB() IOCTL fails.
    4. Due to which, amdgpu_present_check_flip() check fails in DDX
    5. Due to which DDX driver doesn't allow flips (goes to blitting)
    6. Due to which setting Freesync/VRR property fails for PRIME buffers.
    
    So, this patch finally enables Freesync with PRIME buffer offloading.
    
    v2 (chk): instead of just checking the flag we copy it over if the
              exporter is an amdgpu device as well.
    Signed-off-by: NShashank Sharma <shashank.sharma@amd.com>
    Signed-off-by: NChristian König <christian.koenig@amd.com>
    Reviewed-by: NChristian König <christian.koenig@amd.com>
    Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
    e36ccf9a
amdgpu_dma_buf.c 15.9 KB